(no commit message)

[libreriscv.git] / resources.mdwn

diff --git a/resources.mdwn b/resources.mdwn
index 70b607739753272e8adb545d1af784e19f7a69ad..2e3e9065f43b85e88bac6700d8948a6cb3928480 100644 (file)
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -31,6 +31,14 @@ This section is primarily a series of useful links found online
 
 * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
 
+# JTAG
+
+* [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf)
+
+    Abstract
+
+    "The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications."
+
 # RISC-V Instruction Set Architecture
 
 **PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
@@ -162,6 +170,11 @@ although performance is not evaluated.
 
 * [Pixilica 3D Graphical ISA Slides](https://b5792ddd-543e-4dd4-9b97-fe259caf375d.filesusr.com/ugd/841f2a_c8685ced353b4c3ea20dbb993c4d4d18.pdf)
 
+# 3D Graphics Texture compression software and hardware
+
+* [Proprietary Rad Game Tools Oddle Texture Software Compression](https://web.archive.org/web/20200913122043/http://www.radgametools.com/oodle.htm)
+
+* [Blog post by one of the engineers who developed the proprietary Rad Game Tools Oddle Texture Software Compression and the Oodle Kraken decompression software and hardware decoder used in the ps5 ssd](https://archive.vn/oz0pG)
 
 # Various POWER Communities
  - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
@@ -268,6 +281,10 @@ regards to what we specify.  Of course, it is important to do the formal
 verification as a final step in the development process before we produce
 thousands or millions of silicon.
 
+* Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
+
+* Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
+
 Some learning resources I found in the community:
 
 * ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
@@ -338,6 +355,8 @@ Some learning resources I found in the community:
   <https://arxiv.org/pdf/1803.06185.pdf>
 * OpenPOWER Foundation Membership
   <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
+* Clock switching (and formal verification)
+  <https://zipcpu.com/formal/2018/05/31/clkswitch.html>
 
 
 # Real/Physical Projects
@@ -416,3 +435,10 @@ This list auto-generated from a page tag "standards":
 # CircuitJS experiments
 
 * [[resources/high-speed-serdes-in-circuitjs]]
+
+# ASIC Timing and Design flow resources
+
+* <https://www.linkedin.com/pulse/asic-design-flow-introduction-timing-constraints-mahmoud-abdellatif/>
+* <https://www.icdesigntips.com/2020/10/setup-and-hold-time-explained.html>
+* <https://www.vlsiguide.com/2018/07/clock-tree-synthesis-cts.html>
+* <https://en.wikipedia.org/wiki/Frequency_divider>