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@@ -348,11 +348,9 @@ Some learning resources I found in the community:
 
 # Python RTL Tools
 
+* <https://ieeexplore.ieee.org/document/9591456> pylog fpga
+  <https://github.com/hst10/pylog>
 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
-* [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
-  An SOC builder written in Python Migen DSL. Allows you to generate functional
-  RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
-  and parameterizeable CSRs.
 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
 * There is a great guy, Robert Baruch, who has a good
   [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
@@ -361,15 +359,16 @@ Some learning resources I found in the community:
   [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
   online.
   There is now a page [[docs/learning_nmigen]].
-* [Minerva](https://github.com/lambdaconcept/minerva)
-  An SOC written in Python nMigen DSL
-* Minerva example using nmigen-soc
-  <https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
 
 # Other
 
+* Cray-1 Pocket Reference
+  <https://nitter.it/aka_pugs/status/1546576975166201856>
+  <https://ftp.libre-soc.org/cray-1-pocket-ref/>
+  <https://www.computerhistory.org/collections/catalog/102685876>
+* <https://github.com/tdene/synth_opt_adders> Prefix-tree generation scripts
 * <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
 * <https://codeberg.org/tok/librecell> Libre Cell Library
 * <https://wiki.f-si.org/index.php/FSiC2019>
@@ -405,7 +404,9 @@ Some learning resources I found in the community:
 * Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
 * Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
 * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
-<https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf> 
+<https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
+* adrian_b architecture comparison <https://news.ycombinator.com/item?id=24459041>
+* ericandecscent RISC-V <https://libre-soc.org/irclog/%23libre-soc.2021-07-11.log.html>
 
 # Real/Physical Projects
 
@@ -538,5 +539,6 @@ This list auto-generated from a page tag "standards":
      LowRISC is UK based
      https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
     https://cirosantilli.com/x86-paging
+    https://stackoverflow.com/questions/18431261/how-does-x86-paging-work
     http://denninginstitute.com/modules/vm/red/i486page.html
 ```