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[libreriscv.git] / resources.mdwn

diff --git a/resources.mdwn b/resources.mdwn
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+++ b/resources.mdwn
@@ -23,7 +23,8 @@ This section is primarily a series of useful links found online
 
 ## Overview of the user ISA:
 
-[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+* [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+* Power ISA listings <https://power-isa-beta.mybluemix.net/>
 
 ## OpenPOWER OpenFSI Spec (2016)
 
@@ -366,7 +367,6 @@ Some learning resources I found in the community:
   <https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
-* <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
 
 # Other
 
@@ -536,4 +536,6 @@ This list auto-generated from a page tag "standards":
      OpenTitan also uses FuseSoC
      LowRISC is UK based
      https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
+    https://cirosantilli.com/x86-paging
+    http://denninginstitute.com/modules/vm/red/i486page.html
 ```