add 180nm tapeout to progress

[libreriscv.git] / resources.mdwn

diff --git a/resources.mdwn b/resources.mdwn
index 85ef2d2e5ed44998b240f2316e87103c0974a7f6..448b7d2ec663b69fd613380253522cc6b0f6e9c2 100644 (file)
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -281,6 +281,10 @@ regards to what we specify.  Of course, it is important to do the formal
 verification as a final step in the development process before we produce
 thousands or millions of silicon.
 
+* Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
+
+* Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
+
 Some learning resources I found in the community:
 
 * ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
@@ -435,3 +439,4 @@ This list auto-generated from a page tag "standards":
 * <https://www.linkedin.com/pulse/asic-design-flow-introduction-timing-constraints-mahmoud-abdellatif/>
 * <https://www.icdesigntips.com/2020/10/setup-and-hold-time-explained.html>
 * <https://www.vlsiguide.com/2018/07/clock-tree-synthesis-cts.html>
+* <https://en.wikipedia.org/wiki/Frequency_divider>