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[libreriscv.git] / resources.mdwn
index 155c2f2718ff3ec22b4920cfd8d2654f8c4bddb7..46837a2f7c57d8fef7a295208beaaab4bfe5ed4e 100644 (file)
@@ -37,6 +37,15 @@ This section is primarily a series of useful links found online
 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
 
+# Other GPU Specifications
+
+* 
+* https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf 
+* https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf 
+* MALI Midgard
+* Nyuzi
+* VideoCore IV
+* etnaviv
 
 # JTAG
 
@@ -282,6 +291,8 @@ thousands or millions of silicon.
 * Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
 
 * Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
+* Minisail <https://www.isa-afp.org/entries/MiniSail.html> - compiler
+  for SAIL into c
 
 Some learning resources I found in the community:
 
@@ -365,6 +376,7 @@ Some learning resources I found in the community:
 * Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
 * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
 <https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf> 
+
 # Real/Physical Projects
 
 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)