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[libreriscv.git] / resources.mdwn

diff --git a/resources.mdwn b/resources.mdwn
index 2476d2f628a821fba732e286a962a6089cf53df8..4d2ef94cd9df4723ed7e51e8f3b9b35369eec8b3 100644 (file)
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -25,6 +25,12 @@ This section is primarily a series of useful links found online
 
 [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
 
+## OpenPOWER OpenFSI Spec (2016)
+
+* [OpenPOWER OpenFSI Spec](http://openpowerfoundation.org/wp-content/uploads/resources/OpenFSI-spec-100/OpenFSI-spec-20161212.pdf)
+
+* [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
+
 # RISC-V Instruction Set Architecture
 
 **PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
@@ -314,7 +320,7 @@ Some learning resources I found in the community:
   1-deep / 2-register FIFO synchronizer.
 * <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
   Understanding Latency Hiding on GPUs, by Vasily Volkov
-
+* Efabless "Openlane" <https://github.com/efabless/openlane>
 
 # Real/Physical Projects
 
@@ -371,3 +377,11 @@ This list auto-generated from a page tag "standards":
 * [[resources/server-setup/git-mirroring]]
 * [[resources/server-setup/nagios-monitoring]]
 
+# Testbeds
+
+* <https://www.fed4fire.eu/testbeds/>
+
+# Really Useful Stuff
+
+* <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
+* <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>