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@@ -25,6 +25,12 @@ This section is primarily a series of useful links found online
 
 [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
 
+## OpenPOWER OpenFSI Spec (2016)
+
+* [OpenPOWER OpenFSI Spec](http://openpowerfoundation.org/wp-content/uploads/resources/OpenFSI-spec-100/OpenFSI-spec-20161212.pdf)
+
+* [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
+
 # RISC-V Instruction Set Architecture
 
 **PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
@@ -62,11 +68,15 @@ for comparative/informative purposes with regard to Simple-V.
 * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
 
 ## CORDIC and related algorithms
+
+* <https://bugs.libre-soc.org/show_bug.cgi?id=127> research into CORDIC
+* <https://bugs.libre-soc.org/show_bug.cgi?id=208>
 * [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm)
 * [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf)
  - Does not have an easy way of computing tan(x)
 * [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
 * [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
+* <http://www.myhdl.org/docs/examples/sinecomp/> MyHDL version of CORDIC
 
 ## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
 
@@ -80,6 +90,14 @@ it is unfortunately not freely available and requires a payment to
 access. However, each of the Libre RISC-V members already have access
 to the document.
 
+* [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html)
+
+Among other things, has a nice explanation on arithmetic, rounding modes and the sticky bit.
+
+* [What Every Computer Scientist Should Know About Floating-Point Arithmetic](https://docs.oracle.com/cd/E19957-01/806-3568/ncg_goldberg.html)
+
+Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilemma".
+
 ## Past FPU Mistakes to learn from
 
 * [Intel Underestimates Error Bounds by 1.3 quintillion on 
@@ -114,6 +132,11 @@ switching between different accuracy levels, in userspace applications.
 * [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html)
 * [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html)
 
+* OpenCL released the proposed OpenCL 3.0 spec for comments in april 2020
+
+* [Announcement video](https://youtu.be/h0_syTg6TtY)
+* [Announcement video slides (PDF)](https://www.khronos.org/assets/uploads/apis/OpenCL-3.0-Launch-Apr20.pdf)
+
 Note: We are implementing hardware accelerated Vulkan and
 OpenCL while relying on other software projects to translate APIs to
 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
@@ -126,6 +149,11 @@ although performance is not evaluated.
 
 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
 
+* Pixilica is heading up an initiative to create a RISC-V graphical ISA
+
+* [Pixilica 3D Graphical ISA Slides](https://b5792ddd-543e-4dd4-9b97-fe259caf375d.filesusr.com/ugd/841f2a_c8685ced353b4c3ea20dbb993c4d4d18.pdf)
+
+
 # Various POWER Communities
  - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
    The T2080 is a POWER8 chip.
@@ -278,6 +306,21 @@ Some learning resources I found in the community:
 # Other
 
 * <https://wiki.f-si.org/index.php/FSiC2019>
+* <https://fusesoc.net>
+* <https://www.lowrisc.org/open-silicon/>
+* <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
+* <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
+* <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
+  Synchronous Resets? Asynchronous Resets? I am so confused! How will I
+  ever know which to use? by Clifford E. Cummings
+* <http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf>
+  Clock Domain Crossing (CDC) Design & Verification Techniques Using
+  SystemVerilog, by Clifford E. Cummings
+  In particular, see section 5.8.2: Multi-bit CDC signal passing using
+  1-deep / 2-register FIFO synchronizer.
+* <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
+  Understanding Latency Hiding on GPUs, by Vasily Volkov
+* Efabless "Openlane" <https://github.com/efabless/openlane>
 
 # Real/Physical Projects
 
@@ -334,3 +377,11 @@ This list auto-generated from a page tag "standards":
 * [[resources/server-setup/git-mirroring]]
 * [[resources/server-setup/nagios-monitoring]]
 
+# Testbeds
+
+* <https://www.fed4fire.eu/testbeds/>
+
+# Really Useful Stuff
+
+* <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
+* <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>