add missing form to csv tables

[libreriscv.git] / resources.mdwn

diff --git a/resources.mdwn b/resources.mdwn
index 4a99fc590d3d260da9755e33bc0054f71e82e25e..4f71d55bc8bbfefb972fff03b2986768afd1acd1 100644 (file)
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -4,6 +4,11 @@ This page aims to collect all the resources and specifications we need
 in one place for quick access. We will try our best to keep links here
 up-to-date. Feel free to add more links here.
 
+# OpenPOWER ISA
+
+* <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
+* <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
+
 # RISC-V Instruction Set Architecture
 
 The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name
@@ -111,6 +116,16 @@ layout generation flow (RTL-to-GDS).
 
 * <https://theopenroadproject.org/>
 
+# Other RISC-V GPU attempts
+
+* <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
+
+* <http://bjump.org/manycore/>
+
+* <https://resharma.github.io/RISCV32-GPU/>
+
+TODO: Get in touch and discuss collaboration
+
 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
 
 ## RISC-V Tests
@@ -154,9 +169,10 @@ do the paperwork, and pay the relevant fees.
 
 ## Formal Verification
 
-Formal verification of Libre RISC-V ensures that it is bug-free in regards to what we specify.
-Of course, it is important to do the formal verification as a final step in the development process before
-we produce thousands or millions of silicon.
+Formal verification of Libre RISC-V ensures that it is bug-free in
+regards to what we specify.  Of course, it is important to do the formal
+verification as a final step in the development process before we produce
+thousands or millions of silicon.
 
 Some learning resources I found in the community:
 
@@ -171,10 +187,65 @@ ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizze
 
 <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
 
+## Automation
+
+* <https://www.ohwr.org/project/wishbone-gen>
+
+# LLVM
+
+## Adding new instructions:
+
+* <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
+
+# Branch Prediction
+
+* <https://danluu.com/branch-prediction/>
+
+
+# Information Resources and Tutorials
+
+This section is primarily a series of useful links found online
+
+* FSiC2019 <https://wiki.f-si.org/index.php/FSiC2019>
+* Fundamentals to learn to get started [[3d_gpu/tutorial]]
+* <https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers>
+* <https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/>
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html>
+* <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
+* <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
+* <http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>
+* Samuel's KC5 code <http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu>
+* <https://chips4makers.io/blog/>
+* <https://hackaday.io/project/7817-zynqberry>
+* <https://wiki.f-si.org/index.php/FSiC2019>
+* <https://github.com/efabless/raven-picorv32> - <https://efabless.com>
+* <https://efabless.com/design_catalog/default>
+* <https://toyota-ai.ventures/>
+* <https://github.com/lambdaconcept/minerva>
+* <https://en.wikipedia.org/wiki/Liskov_substitution_principle>
+* <https://en.wikipedia.org/wiki/Principle_of_least_astonishment>
+* <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
+* <https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md>
+* <https://mshahrad.github.io/openpiton-asplos16.html>
+* <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
+* <http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/>
+* <http://www.crnhq.org/12-Skills-Summary.aspx?rw=c>
+* <http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02>
+* <https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf>
+* <http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf>
+* <https://youtu.be/o5Ihqg72T3c>
+* <http://flopoco.gforge.inria.fr/>
+* Fundamentals of Modern VLSI Devices <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
+
+# Analog Simulation
+
+* <https://github.com/Isotel/mixedsim>
+* <http://www.vlsiacademy.org/open-source-cad-tools.html>
+* <http://ngspice.sourceforge.net/adms.html>
+* <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
+
 # Libre-RISC-V Standards
 
 This list auto-generated from a page tag "standards":
 
 [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
-
-