* [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
+# Communities
+
+* <https://www.reddit.com/r/OpenPOWER/>
+* <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
+* <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
+
+
# JTAG
* [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf)
* [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md)
Note: As far as I know, we aren't using the RISC-V V Extension directly
-at the moment. However, there are many wiki pages that make a reference
+at the moment (correction: we were never going to). However, there are many wiki pages that make a reference
to the V extension so it would be good to include it here as a reference
for comparative/informative purposes with regard to Simple-V.
+<https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>
# Radix MMU
- [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
# RTL Arithmetic SQRT, FPU etc.
+## Wallace vs Dadda Multipliers
+
+* [Paper comparing efficiency of Wallace and Dadda Multipliers in RTL implementations (clicking will download the pdf from archive.org)](https://web.archive.org/web/20180717013227/http://ieeemilestones.ethw.org/images/d/db/A_comparison_of_Dadda_and_Wallace_multiplier_delays.pdf)
+
## Sqrt
* [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
* [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
* [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
* [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
* <http://www.myhdl.org/docs/examples/sinecomp/> MyHDL version of CORDIC
+* <https://dspguru.com/dsp/faqs/cordic/>
## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
* [Intel Underestimates Error Bounds by 1.3 quintillion on
Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
* [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
-
+* How not to design an ISA
+ <https://player.vimeo.com/video/450406346>
+ Meester Forsyth <http://eelpi.gotdns.org/>
# Khronos Standards
The Khronos Group creates open standards for authoring and acceleration
* [Pixilica 3D Graphical ISA Slides](https://b5792ddd-543e-4dd4-9b97-fe259caf375d.filesusr.com/ugd/841f2a_c8685ced353b4c3ea20dbb993c4d4d18.pdf)
+# 3D Graphics Texture compression software and hardware
+
+* [Proprietary Rad Game Tools Oddle Texture Software Compression](https://web.archive.org/web/20200913122043/http://www.radgametools.com/oodle.htm)
+
+* [Blog post by one of the engineers who developed the proprietary Rad Game Tools Oddle Texture Software Compression and the Oodle Kraken decompression software and hardware decoder used in the ps5 ssd](https://archive.vn/oz0pG)
# Various POWER Communities
- [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
verification as a final step in the development process before we produce
thousands or millions of silicon.
+* Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
+
+* Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
+
Some learning resources I found in the community:
* ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
online.
* [Minerva](https://github.com/lambdaconcept/minerva)
An SOC written in Python nMigen DSL
+* Minerva example using nmigen-soc
+ <https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
* [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
* <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
* <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
# Other
+* <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
+* <https://codeberg.org/tok/librecell> Libre Cell Library
* <https://wiki.f-si.org/index.php/FSiC2019>
* <https://fusesoc.net>
* <https://www.lowrisc.org/open-silicon/>
<https://arxiv.org/pdf/1803.06185.pdf>
* OpenPOWER Foundation Membership
<https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
-
-
+* Clock switching (and formal verification)
+ <https://zipcpu.com/formal/2018/05/31/clkswitch.html>
+* Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
+* Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
+* Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
+<https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
# Real/Physical Projects
* [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
# CircuitJS experiments
* [[resources/high-speed-serdes-in-circuitjs]]
+
+# ASIC Timing and Design flow resources
+
+* <https://www.linkedin.com/pulse/asic-design-flow-introduction-timing-constraints-mahmoud-abdellatif/>
+* <https://www.icdesigntips.com/2020/10/setup-and-hold-time-explained.html>
+* <https://www.vlsiguide.com/2018/07/clock-tree-synthesis-cts.html>
+* <https://en.wikipedia.org/wiki/Frequency_divider>
+
+# Geometric Haskell Library
+
+* <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/GeometricAlgebra.hs>
+* <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/PGA.hs>
+* <https://arxiv.org/pdf/1501.06511.pdf>
+* <https://bivector.net/index.html>
projects / libreriscv.git / blobdiff