* [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
+# Communities
+
+* <https://www.reddit.com/r/OpenPOWER/>
+* <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
+* <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
+
+
# JTAG
* [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf)
* [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md)
Note: As far as I know, we aren't using the RISC-V V Extension directly
-at the moment. However, there are many wiki pages that make a reference
+at the moment (correction: we were never going to). However, there are many wiki pages that make a reference
to the V extension so it would be good to include it here as a reference
for comparative/informative purposes with regard to Simple-V.
+<https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>
# Radix MMU
- [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
# RTL Arithmetic SQRT, FPU etc.
+## Wallace vs Dadda Multipliers
+
+* [Paper comparing efficiency of Wallace and Dadda Multipliers in RTL implementations (clicking will download the pdf from archive.org)](https://web.archive.org/web/20180717013227/http://ieeemilestones.ethw.org/images/d/db/A_comparison_of_Dadda_and_Wallace_multiplier_delays.pdf)
+
## Sqrt
* [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
* [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
* [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
* [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
* <http://www.myhdl.org/docs/examples/sinecomp/> MyHDL version of CORDIC
+* <https://dspguru.com/dsp/faqs/cordic/>
## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
* [Intel Underestimates Error Bounds by 1.3 quintillion on
Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
* [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
-
+* How not to design an ISA
+ <https://player.vimeo.com/video/450406346>
+ Meester Forsyth <http://eelpi.gotdns.org/>
# Khronos Standards
The Khronos Group creates open standards for authoring and acceleration
# Other
+* <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
+* <https://codeberg.org/tok/librecell> Libre Cell Library
* <https://wiki.f-si.org/index.php/FSiC2019>
* <https://fusesoc.net>
* <https://www.lowrisc.org/open-silicon/>
* <https://www.icdesigntips.com/2020/10/setup-and-hold-time-explained.html>
* <https://www.vlsiguide.com/2018/07/clock-tree-synthesis-cts.html>
* <https://en.wikipedia.org/wiki/Frequency_divider>
+
+# Geometric Haskell Library
+
+* <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/GeometricAlgebra.hs>
+* <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/PGA.hs>
+* <https://arxiv.org/pdf/1501.06511.pdf>
+* <https://bivector.net/index.html>
projects / libreriscv.git / blobdiff