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@@ -65,6 +65,10 @@ for comparative/informative purposes with regard to Simple-V.
 ## D-Cache Possible Optimizations papers and links
 - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
 
+# BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
+- [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
+- [Url to PDF of paper on author's website (clicking will download the pdf)](https://adwaitjog.github.io/docs/pdf/sharedl1-pact20.pdf)
+
 
 # RTL Arithmetic SQRT, FPU etc.
 
@@ -328,6 +332,8 @@ Some learning resources I found in the community:
 * Efabless "Openlane" <https://github.com/efabless/openlane>
 * Co-simulation plugin for verilator, transferring to ECP5
   <https://github.com/vmware/cascade>
+* Multi-read/write ported memories
+  <https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html>
 
 
 # Real/Physical Projects
@@ -393,3 +399,16 @@ This list auto-generated from a page tag "standards":
 
 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>
+
+# Digilent Arty
+
+* https://store.digilentinc.com/pmod-sf3-32-mb-serial-nor-flash/
+* https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/
+* https://store.digilentinc.com/pmod-vga-video-graphics-array/
+* https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
+* https://store.digilentinc.com/pmod-rtcc-real-time-clock-calendar/
+* https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
+
+# CircuitJS experiments
+
+* [[resources/high-speed-serdes-in-circuitjs]]