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@@ -75,8 +75,8 @@ switching between different accuracy levels, in userspace applications.
 * OpenCL 2.2 SPIR-V Environment Specification:
   <https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html>
 
-Note: We are implementing hardware accelerated Vulkan (and possibly
-OpenCL) while relying on other software projects to translate APIs to
+Note: We are implementing hardware accelerated Vulkan and
+OpenCL while relying on other software projects to translate APIs to
 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
 
 # Graphics and Compute API Stack
@@ -111,6 +111,16 @@ layout generation flow (RTL-to-GDS).
 
 * <https://theopenroadproject.org/>
 
+# Other RISC-V GPU attempts
+
+* <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
+
+* <http://bjump.org/manycore/>
+
+* <https://resharma.github.io/RISCV32-GPU/>
+
+TODO: Get in touch and discuss collaboration
+
 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
 
 ## RISC-V Tests
@@ -152,3 +162,38 @@ MAJOR NOTE: We are **not** allowed to say we are compliant with any of
 the Khronos standards until we actually make an official submission,
 do the paperwork, and pay the relevant fees.
 
+## Formal Verification
+
+Formal verification of Libre RISC-V ensures that it is bug-free in
+regards to what we specify.  Of course, it is important to do the formal
+verification as a final step in the development process before we produce
+thousands or millions of silicon.
+
+Some learning resources I found in the community:
+
+* ZipCPU: <http://zipcpu.com/>
+
+ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizzes/slides: <http://zipcpu.com/tutorial/>
+
+
+* Western Digital's SweRV CPU blog (I recommend looking at all their posts): <https://tomverbeure.github.io/>
+
+<https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
+
+<https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
+
+## Automation
+
+* <https://www.ohwr.org/project/wishbone-gen>
+
+# Libre-RISC-V Standards
+
+This list auto-generated from a page tag "standards":
+
+[[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
+
+# LLVM
+
+## Adding new instructions:
+
+* <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>