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[libreriscv.git] / resources.mdwn

diff --git a/resources.mdwn b/resources.mdwn
index ed96acbaa6f09c15e425ec581774874c6756138d..9fee96421bc7065692c7b177f4c0559271d2e9a2 100644 (file)
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -23,7 +23,8 @@ This section is primarily a series of useful links found online
 
 ## Overview of the user ISA:
 
-[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+* [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+* Power ISA listings <https://power-isa-beta.mybluemix.net/>
 
 ## OpenPOWER OpenFSI Spec (2016)
 
@@ -48,7 +49,7 @@ This section is primarily a series of useful links found online
 * https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf 
 * https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf 
 * MALI Midgard
-* Nyuzi
+* [Nyuzi](https://github.com/jbush001/NyuziProcessor)
 * VideoCore IV
 * etnaviv
 
@@ -65,6 +66,9 @@ This section is primarily a series of useful links found online
 
 # D-Cache
 
+- [A Primer on Memory Consistency and Cache Coherence
+](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049)
+
 ## D-Cache Possible Optimizations papers and links
 - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
 - [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of
@@ -217,6 +221,11 @@ see [[conferences]]
 Note: The rest of LIP6's website is in French, but there is a UK flag
 in the corner that gives the English version.
 
+# Logical Equivalence and extraction
+
+* NETGEN
+* CVC https://github.com/d-m-bailey/cvc
+
 # Klayout
 
 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
@@ -315,6 +324,18 @@ Some learning resources I found in the community:
 
 * <https://www.ohwr.org/project/wishbone-gen>
 
+# Bus Architectures
+
+* Avalon <https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf>
+* CXM <https://www.computeexpresslink.org/download-the-specification>
+
+# Vector Processors
+
+* THOR <https://github.com/robfinch/Thor/blob/main/Thor2021/doc/Thor2021.pdf>
+* NEC SX-Aurora
+* RVV
+* MRISC32 <https://github.com/mrisc32/mrisc32>
+
 # LLVM
 
 ## Adding new instructions:
@@ -346,7 +367,6 @@ Some learning resources I found in the community:
   <https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
-* <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
 
 # Other
 
@@ -357,6 +377,8 @@ Some learning resources I found in the community:
 * <https://www.lowrisc.org/open-silicon/>
 * <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
 * <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
+* <https://github.com/Ben1152000/sootty> - console-based vcd viewer
+* <https://github.com/ics-jku/wal> - Waveform Analysis
 * <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
   Synchronous Resets? Asynchronous Resets? I am so confused! How will I
   ever know which to use? by Clifford E. Cummings
@@ -515,4 +537,6 @@ This list auto-generated from a page tag "standards":
      OpenTitan also uses FuseSoC
      LowRISC is UK based
      https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
+    https://cirosantilli.com/x86-paging
+    http://denninginstitute.com/modules/vm/red/i486page.html
 ```