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[libreriscv.git] / resources.mdwn

diff --git a/resources.mdwn b/resources.mdwn
index ee4ba3a3c1669648ae340b5f792731a3145fc2d4..a647c9bbaf4bbe1f67e7e48376d75dcae665cd77 100644 (file)
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -36,7 +36,17 @@ This section is primarily a series of useful links found online
 * <https://www.reddit.com/r/OpenPOWER/>
 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
+* Open tape-out mailing list <https://groups.google.com/a/opentapeout.dev/g/mailinglist>
 
+# Other GPU Specifications
+
+* 
+* https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf 
+* https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf 
+* MALI Midgard
+* Nyuzi
+* VideoCore IV
+* etnaviv
 
 # JTAG
 
@@ -93,7 +103,7 @@ course, we will follow it as well for interoperability.
 
 Note: Even though this is such an important standard used by everyone,
 it is unfortunately not freely available and requires a payment to
-access. However, each of the Libre RISC-V members already have access
+access. However, each of the Libre-SOC members already have access
 to the document.
 
 * [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html)
@@ -112,6 +122,7 @@ Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2
 * How not to design an ISA
  <https://player.vimeo.com/video/450406346>
   Meester Forsyth <http://eelpi.gotdns.org/>
+
 # Khronos Standards
 
 The Khronos Group creates open standards for authoring and acceleration
@@ -189,14 +200,10 @@ although performance is not evaluated.
 
 # Conferences
 
-## Free Silicon Conference
+see [[conferences]]
 
-The conference brought together experts and enthusiasts who want to build
-a complete Free and Open Source CAD ecosystem for designing analog and
-digital integrated circuits.  The conference covered the full spectrum of
-the design process, from system architecture, to layout and verification.
 
-* <https://wiki.f-si.org/index.php/FSiC2019#Foundries.2C_PDKs_and_cell_libraries>
+# Coriolis2
 
 * LIP6's Coriolis - a set of backend design tools:
   <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
@@ -204,8 +211,14 @@ the design process, from system architecture, to layout and verification.
 Note: The rest of LIP6's website is in French, but there is a UK flag
 in the corner that gives the English version.
 
+# Klayout
+
 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
 
+# image to GDS-II
+
+* https://nazca-design.org/convert-image-to-gds/
+ 
 # The OpenROAD Project
 
 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
@@ -279,6 +292,8 @@ thousands or millions of silicon.
 * Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
 
 * Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
+* Minisail <https://www.isa-afp.org/entries/MiniSail.html> - compiler
+  for SAIL into c
 
 Some learning resources I found in the community:
 
@@ -318,6 +333,7 @@ Some learning resources I found in the community:
   [the code](https://github.com/RobertBaruch/n6800) and
   [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
   online.
+  There is now a page [[docs/learning_nmigen]].
 * [Minerva](https://github.com/lambdaconcept/minerva)
   An SOC written in Python nMigen DSL
 * Minerva example using nmigen-soc
@@ -347,7 +363,7 @@ Some learning resources I found in the community:
   Understanding Latency Hiding on GPUs, by Vasily Volkov
 * Efabless "Openlane" <https://github.com/efabless/openlane>
 * example of openlane with nmigen
-  <https://gist.github.com/lethalbit/e65e296bc6a3810280d1b256c9df591b>
+  <https://github.com/lethalbit/nmigen/tree/openlane>
 * Co-simulation plugin for verilator, transferring to ECP5
   <https://github.com/vmware/cascade>
 * Multi-read/write ported memories
@@ -362,6 +378,7 @@ Some learning resources I found in the community:
 * Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
 * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
 <https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf> 
+
 # Real/Physical Projects
 
 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)