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[libreriscv.git] / resources.mdwn

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@@ -21,6 +21,10 @@ This section is primarily a series of useful links found online
 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
 
+## Overview of the user ISA:
+
+[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+
 # RISC-V Instruction Set Architecture
 
 **PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
@@ -257,6 +261,9 @@ ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizze
   RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
   and parameterizeable CSRs.
 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
+
+* There is a great guy, Robert Baruch, who has a good [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen. He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put [the code](https://github.com/RobertBaruch/n6800) and [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw) online.
+
 * [Minerva](https://github.com/lambdaconcept/minerva)
   An SOC written in Python nMigen DSL