* [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
* [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
+## Overview of the user ISA:
+
+[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+
# RISC-V Instruction Set Architecture
**PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
* [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
* [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
+## CORDIC and related algorithms
+* [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm)
+* [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf)
+ - Does not have an easy way of computing tan(x)
+* [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
+* [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
+
## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
Almost all modern computers follow the IEEE Floating-Point Standard. Of
access. However, each of the Libre RISC-V members already have access
to the document.
+## Past FPU Mistakes to learn from
+
+* [Intel Underestimates Error Bounds by 1.3 quintillion on
+Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
+* [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
+
# Khronos Standards
The Khronos Group creates open standards for authoring and acceleration
RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
and parameterizeable CSRs.
* [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
+
+* There is a great guy, Robert Baruch, who has a good [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen. He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put [the code](https://github.com/RobertBaruch/n6800) and [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw) online.
+
* [Minerva](https://github.com/lambdaconcept/minerva)
An SOC written in Python nMigen DSL
# Server setup
+[[resources/server-setup/web-server]]
+
[[resources/server-setup/git-mirroring]]
+
+[[resources/server-setup/nagios-monitoring]]
+