## Overview of the user ISA:
-[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+* [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+* Power ISA listings <https://power-isa-beta.mybluemix.net/>
## OpenPOWER OpenFSI Spec (2016)
* [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
+# Energy-efficient cores
+
+* https://arxiv.org/abs/2002.10143
+
# Communities
* <https://www.reddit.com/r/OpenPOWER/>
* <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
* <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
+* Open tape-out mailing list <https://groups.google.com/a/opentapeout.dev/g/mailinglist>
# Other GPU Specifications
* https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf
* https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf
* MALI Midgard
-* Nyuzi
+* [Nyuzi](https://github.com/jbush001/NyuziProcessor)
* VideoCore IV
* etnaviv
# D-Cache
+- [A Primer on Memory Consistency and Cache Coherence
+](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049)
+
## D-Cache Possible Optimizations papers and links
- [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
+- [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of
+Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901)
# BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
- [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
Note: The rest of LIP6's website is in French, but there is a UK flag
in the corner that gives the English version.
+# Logical Equivalence and extraction
+
+* NETGEN
+* CVC https://github.com/d-m-bailey/cvc
+
# Klayout
* KLayout - Layout viewer and editor: <https://www.klayout.de/>
* <https://www.ohwr.org/project/wishbone-gen>
+# Bus Architectures
+
+* Avalon <https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf>
+* CXM <https://www.computeexpresslink.org/download-the-specification>
+
+# Vector Processors
+
+* THOR <https://github.com/robfinch/Thor/blob/main/Thor2021/doc/Thor2021.pdf>
+* NEC SX-Aurora
+* RVV
+* MRISC32 <https://github.com/mrisc32/mrisc32>
+
# LLVM
## Adding new instructions:
[the code](https://github.com/RobertBaruch/n6800) and
[instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
online.
+ There is now a page [[docs/learning_nmigen]].
* [Minerva](https://github.com/lambdaconcept/minerva)
An SOC written in Python nMigen DSL
* Minerva example using nmigen-soc
<https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
* [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
* <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
-* <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
# Other
* <https://www.lowrisc.org/open-silicon/>
* <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
* <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
+* <https://github.com/ics-jku/wal> - Waveform Analysis
* <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
Synchronous Resets? Asynchronous Resets? I am so confused! How will I
ever know which to use? by Clifford E. Cummings