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@@ -325,6 +325,8 @@ Some learning resources I found in the community:
   online.
 * [Minerva](https://github.com/lambdaconcept/minerva)
   An SOC written in Python nMigen DSL
+* Minerva example using nmigen-soc
+  <https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
@@ -357,8 +359,10 @@ Some learning resources I found in the community:
   <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
 * Clock switching (and formal verification)
   <https://zipcpu.com/formal/2018/05/31/clkswitch.html>
-
-
+* Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
+* Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
+* Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
+<https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf> 
 # Real/Physical Projects
 
 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)