add wishbone slave generator

[libreriscv.git] / resources.mdwn

diff --git a/resources.mdwn b/resources.mdwn
index 4a99fc590d3d260da9755e33bc0054f71e82e25e..ba7e0843169d37ac1083cc3558d5e6b73e658317 100644 (file)
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -111,6 +111,16 @@ layout generation flow (RTL-to-GDS).
 
 * <https://theopenroadproject.org/>
 
+# Other RISC-V GPU attempts
+
+* <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
+
+* <http://bjump.org/manycore/>
+
+* <https://resharma.github.io/RISCV32-GPU/>
+
+TODO: Get in touch and discuss collaboration
+
 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
 
 ## RISC-V Tests
@@ -154,9 +164,10 @@ do the paperwork, and pay the relevant fees.
 
 ## Formal Verification
 
-Formal verification of Libre RISC-V ensures that it is bug-free in regards to what we specify.
-Of course, it is important to do the formal verification as a final step in the development process before
-we produce thousands or millions of silicon.
+Formal verification of Libre RISC-V ensures that it is bug-free in
+regards to what we specify.  Of course, it is important to do the formal
+verification as a final step in the development process before we produce
+thousands or millions of silicon.
 
 Some learning resources I found in the community:
 
@@ -171,6 +182,10 @@ ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizze
 
 <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
 
+## Automation
+
+* <https://www.ohwr.org/project/wishbone-gen>
+
 # Libre-RISC-V Standards
 
 This list auto-generated from a page tag "standards":