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[libreriscv.git] / resources.mdwn

diff --git a/resources.mdwn b/resources.mdwn
index b221a6d9a1d6df55174a27fec2e98bd9b6aa4609..ba7e0843169d37ac1083cc3558d5e6b73e658317 100644 (file)
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -4,13 +4,6 @@ This page aims to collect all the resources and specifications we need
 in one place for quick access. We will try our best to keep links here
 up-to-date. Feel free to add more links here.
 
-# Libre-RISC-V Standards
-
-This list auto-generated from a page tag "standards":
-
-[[!inline pages="tagged(standards)" actions="no" quick="yes"]]
-
-
 # RISC-V Instruction Set Architecture
 
 The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name
@@ -118,6 +111,16 @@ layout generation flow (RTL-to-GDS).
 
 * <https://theopenroadproject.org/>
 
+# Other RISC-V GPU attempts
+
+* <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
+
+* <http://bjump.org/manycore/>
+
+* <https://resharma.github.io/RISCV32-GPU/>
+
+TODO: Get in touch and discuss collaboration
+
 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
 
 ## RISC-V Tests
@@ -160,9 +163,11 @@ the Khronos standards until we actually make an official submission,
 do the paperwork, and pay the relevant fees.
 
 ## Formal Verification
-Formal verification of Libre RISC-V ensures that it is bug-free in regards to what we specify.
-Of course, it is important to do the formal verification as a final step in the development process before
-we produce thousands or millions of silicon.
+
+Formal verification of Libre RISC-V ensures that it is bug-free in
+regards to what we specify.  Of course, it is important to do the formal
+verification as a final step in the development process before we produce
+thousands or millions of silicon.
 
 Some learning resources I found in the community:
 
@@ -177,3 +182,14 @@ ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizze
 
 <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
 
+## Automation
+
+* <https://www.ohwr.org/project/wishbone-gen>
+
+# Libre-RISC-V Standards
+
+This list auto-generated from a page tag "standards":
+
+[[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
+
+