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@@ -20,6 +20,7 @@ This section is primarily a series of useful links found online
 
 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
+* Virginia Tech course <https://github.com/w-feng/CompArch-MIPS-POWER>
 
 ## Overview of the user ISA:
 
@@ -36,6 +37,10 @@ This section is primarily a series of useful links found online
 
 * https://arxiv.org/abs/2002.10143
 
+# Open Access Publication locations
+
+* <https://open-research-europe.ec.europa.eu/browse/engineering-and-technology>
+
 # Communities
 
 * <https://www.reddit.com/r/OpenPOWER/>
@@ -43,6 +48,16 @@ This section is primarily a series of useful links found online
 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
 * Open tape-out mailing list <https://groups.google.com/a/opentapeout.dev/g/mailinglist>
 
+# ppc64 ELF ABI
+
+* EABI 1.9 supplement <https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.html>
+* https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.pdf
+
+# Similar concepts
+
+* <https://www.tdx.cat/bitstream/handle/10803/674224/TCRL1de1.pdf> Vector registers may be
+  made "ultra-wide" (SX Aurora / Cray)
+
 # Other GPU Specifications
 
 * 
@@ -320,6 +335,15 @@ Some learning resources I found in the community:
 * <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
 * <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
 
+VAMP CPU
+
+* Formal verification of a fully IEEE compliant floating point unit
+<https://publikationen.sulb.uni-saarland.de/bitstream/20.500.11880/25760/1/ChristianJacobi_ProfDrWolfgangJPaul.pdf>
+* <https://www-wjp.cs.uni-sb.de/forschung/projekte/VAMP/?lang=en>
+* the PVS/hw subfolder is under the 2-clause BSD license:
+    <https://www-wjp.cs.uni-sb.de/forschung/projekte/VAMP/PVS/hw/COPYRIGHT>
+* <https://alastairreid.github.io/RelatedWork/papers/beyer:ijsttt:2006/>
+
 ## Automation
 
 * <https://www.ohwr.org/project/wishbone-gen>
@@ -364,6 +388,11 @@ Some learning resources I found in the community:
 
 # Other
 
+* <https://github.com/chrische-xx/mpw7> 10-bit SAR ADC
+* Cray-1 Pocket Reference
+  <https://nitter.it/aka_pugs/status/1546576975166201856>
+  <https://ftp.libre-soc.org/cray-1-pocket-ref/>
+  <https://www.computerhistory.org/collections/catalog/102685876>
 * <https://github.com/tdene/synth_opt_adders> Prefix-tree generation scripts
 * <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
 * <https://codeberg.org/tok/librecell> Libre Cell Library
@@ -402,6 +431,7 @@ Some learning resources I found in the community:
 * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
 <https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
 * adrian_b architecture comparison <https://news.ycombinator.com/item?id=24459041>
+* ericandecscent RISC-V <https://libre-soc.org/irclog/%23libre-soc.2021-07-11.log.html>
 
 # Real/Physical Projects
 
@@ -509,9 +539,17 @@ This list auto-generated from a page tag "standards":
 * <https://arxiv.org/pdf/1501.06511.pdf>
 * <https://bivector.net/index.html>
 
+# Handy Compiler Algorithms for SimpleV
+
+Requires aligned registers:
+* [Graph Coloring Register Allocation for Processors with Multi-Register Operands](https://dl.acm.org/doi/pdf/10.1145/93548.93552)
+More general:
+* [Retargetable Graph-Coloring Register Allocation for Irregular Architectures](https://user.it.uu.se/~svenolof/wpo/AllocSCOPES2003.20030626b.pdf)
+
 # TODO investigate
 
 ```
+     https://www.nextplatform.com/2022/08/22/the-expanding-cxl-memory-hierarchy-is-inevitable-and-good-enough/
      https://github.com/idea-fasoc/OpenFASOC
      https://www.quicklogic.com/2020/06/18/the-tipping-point/
      https://www.quicklogic.com/blog/