* [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
* [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
+* Virginia Tech course <https://github.com/w-feng/CompArch-MIPS-POWER>
## Overview of the user ISA:
-[Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+* [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
+* Power ISA listings <https://power-isa-beta.mybluemix.net/>
## OpenPOWER OpenFSI Spec (2016)
* [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
+# Energy-efficient cores
+
+* https://arxiv.org/abs/2002.10143
+
# Communities
* <https://www.reddit.com/r/OpenPOWER/>
* <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
* Open tape-out mailing list <https://groups.google.com/a/opentapeout.dev/g/mailinglist>
+# ppc64 ELF ABI
+
+* EABI 1.9 supplement <https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.html>
+* https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.pdf
+
# Other GPU Specifications
*
* https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf
* https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf
* MALI Midgard
-* Nyuzi
+* [Nyuzi](https://github.com/jbush001/NyuziProcessor)
* VideoCore IV
* etnaviv
# D-Cache
+- [A Primer on Memory Consistency and Cache Coherence
+](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049)
+
## D-Cache Possible Optimizations papers and links
- [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
+- [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of
+Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901)
# BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
- [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
Note: The rest of LIP6's website is in French, but there is a UK flag
in the corner that gives the English version.
+# Logical Equivalence and extraction
+
+* NETGEN
+* CVC https://github.com/d-m-bailey/cvc
+
# Klayout
* KLayout - Layout viewer and editor: <https://www.klayout.de/>
* <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
* <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
+VAMP CPU
+
+* Formal verification of a fully IEEE compliant floating point unit
+<https://publikationen.sulb.uni-saarland.de/bitstream/20.500.11880/25760/1/ChristianJacobi_ProfDrWolfgangJPaul.pdf>
+* <https://www-wjp.cs.uni-sb.de/forschung/projekte/VAMP/?lang=en>
+* the PVS/hw subfolder is under the 2-clause BSD license:
+ <https://www-wjp.cs.uni-sb.de/forschung/projekte/VAMP/PVS/hw/COPYRIGHT>
+* <https://alastairreid.github.io/RelatedWork/papers/beyer:ijsttt:2006/>
+
## Automation
* <https://www.ohwr.org/project/wishbone-gen>
+# Bus Architectures
+
+* Avalon <https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf>
+* CXM <https://www.computeexpresslink.org/download-the-specification>
+
+# Vector Processors
+
+* THOR <https://github.com/robfinch/Thor/blob/main/Thor2021/doc/Thor2021.pdf>
+* NEC SX-Aurora
+* RVV
+* MRISC32 <https://github.com/mrisc32/mrisc32>
+
# LLVM
## Adding new instructions:
# Python RTL Tools
+* <https://ieeexplore.ieee.org/document/9591456> pylog fpga
+ <https://github.com/hst10/pylog>
* [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
-* [LiTeX](https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers)
- An SOC builder written in Python Migen DSL. Allows you to generate functional
- RTL for a SOC configured with cache, a RISCV core, ethernet, DRAM support,
- and parameterizeable CSRs.
* [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
* There is a great guy, Robert Baruch, who has a good
[tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
[instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
online.
There is now a page [[docs/learning_nmigen]].
-* [Minerva](https://github.com/lambdaconcept/minerva)
- An SOC written in Python nMigen DSL
-* Minerva example using nmigen-soc
- <https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
* [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
* <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
-* <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
# Other
+* <https://github.com/chrische-xx/mpw7> 10-bit SAR ADC
+* Cray-1 Pocket Reference
+ <https://nitter.it/aka_pugs/status/1546576975166201856>
+ <https://ftp.libre-soc.org/cray-1-pocket-ref/>
+ <https://www.computerhistory.org/collections/catalog/102685876>
+* <https://github.com/tdene/synth_opt_adders> Prefix-tree generation scripts
* <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
* <https://codeberg.org/tok/librecell> Libre Cell Library
* <https://wiki.f-si.org/index.php/FSiC2019>
* <https://www.lowrisc.org/open-silicon/>
* <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
* <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
+* <https://github.com/Ben1152000/sootty> - console-based vcd viewer
+* <https://github.com/ics-jku/wal> - Waveform Analysis
* <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
Synchronous Resets? Asynchronous Resets? I am so confused! How will I
ever know which to use? by Clifford E. Cummings
* Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
* Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
* Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
-<https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
+<https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
+* adrian_b architecture comparison <https://news.ycombinator.com/item?id=24459041>
+* ericandecscent RISC-V <https://libre-soc.org/irclog/%23libre-soc.2021-07-11.log.html>
# Real/Physical Projects
* <https://arxiv.org/pdf/1501.06511.pdf>
* <https://bivector.net/index.html>
+# Handy Compiler Algorithms for SimpleV
+
+Requires aligned registers:
+* [Graph Coloring Register Allocation for Processors with Multi-Register Operands](https://dl.acm.org/doi/pdf/10.1145/93548.93552)
+More general:
+* [Retargetable Graph-Coloring Register Allocation for Irregular Architectures](https://user.it.uu.se/~svenolof/wpo/AllocSCOPES2003.20030626b.pdf)
+
# TODO investigate
```
+ https://www.nextplatform.com/2022/08/22/the-expanding-cxl-memory-hierarchy-is-inevitable-and-good-enough/
https://github.com/idea-fasoc/OpenFASOC
https://www.quicklogic.com/2020/06/18/the-tipping-point/
https://www.quicklogic.com/blog/
OpenTitan also uses FuseSoC
LowRISC is UK based
https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
+ https://cirosantilli.com/x86-paging
+ https://stackoverflow.com/questions/18431261/how-does-x86-paging-work
+ http://denninginstitute.com/modules/vm/red/i486page.html
```
projects / libreriscv.git / blobdiff