* [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
+# Communities
+
+* <https://www.reddit.com/r/OpenPOWER/>
+* <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
+* <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
+
+
# JTAG
* [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf)
* [RISC-V Supervisor Binary Interface Specification](https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md)
Note: As far as I know, we aren't using the RISC-V V Extension directly
-at the moment. However, there are many wiki pages that make a reference
+at the moment (correction: we were never going to). However, there are many wiki pages that make a reference
to the V extension so it would be good to include it here as a reference
for comparative/informative purposes with regard to Simple-V.
+<https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vsetvlivsetvl-instructions>
# Radix MMU
- [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
# RTL Arithmetic SQRT, FPU etc.
+## Wallace vs Dadda Multipliers
+
+* [Paper comparing efficiency of Wallace and Dadda Multipliers in RTL implementations (clicking will download the pdf from archive.org)](https://web.archive.org/web/20180717013227/http://ieeemilestones.ethw.org/images/d/db/A_comparison_of_Dadda_and_Wallace_multiplier_delays.pdf)
+
## Sqrt
* [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
* [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
+* [Fast Calculation of Cube and Inverse Cube Roots Using a Magic Constant and Its Implementation on Microcontrollers (clicking will download the pdf)](https://res.mdpi.com/d_attachment/energies/energies-14-01058/article_deploy/energies-14-01058-v2.pdf)
+* [Modified Fast Inverse Square Root and Square Root Approximation Algorithms: The Method of Switching Magic Constants (clicking will download the pdf)](https://res.mdpi.com/d_attachment/computation/computation-09-00021/article_deploy/computation-09-00021-v3.pdf)
+
## CORDIC and related algorithms
* [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
* [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
* <http://www.myhdl.org/docs/examples/sinecomp/> MyHDL version of CORDIC
+* <https://dspguru.com/dsp/faqs/cordic/>
## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
* [Intel Underestimates Error Bounds by 1.3 quintillion on
Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
* [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
-
+* How not to design an ISA
+ <https://player.vimeo.com/video/450406346>
+ Meester Forsyth <http://eelpi.gotdns.org/>
# Khronos Standards
The Khronos Group creates open standards for authoring and acceleration
online.
* [Minerva](https://github.com/lambdaconcept/minerva)
An SOC written in Python nMigen DSL
+* Minerva example using nmigen-soc
+ <https://github.com/jfng/minerva-examples/blob/master/hello/core.py>
* [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
* <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
* <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
# Other
+* <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
+* <https://codeberg.org/tok/librecell> Libre Cell Library
* <https://wiki.f-si.org/index.php/FSiC2019>
* <https://fusesoc.net>
* <https://www.lowrisc.org/open-silicon/>
* <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
Understanding Latency Hiding on GPUs, by Vasily Volkov
* Efabless "Openlane" <https://github.com/efabless/openlane>
+* example of openlane with nmigen
+ <https://gist.github.com/lethalbit/e65e296bc6a3810280d1b256c9df591b>
* Co-simulation plugin for verilator, transferring to ECP5
<https://github.com/vmware/cascade>
* Multi-read/write ported memories
<https://zipcpu.com/formal/2018/05/31/clkswitch.html>
* Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
* Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
-
+* Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
+<https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
# Real/Physical Projects
* [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
* [[resources/high-speed-serdes-in-circuitjs]]
+# Logic Simulator 2
+* <https://github.com/dkilfoyle/logic2>
+[Live web version](https://dkilfoyle.github.io/logic2/)
+
+> ## Features
+> 1. Micro-subset verilog-like DSL for coding the array of logic gates (parsed using Antlr)
+> 2. Monaco-based code editor with automatic linting/error reporting, smart indentation, code folding, hints
+> 3. IDE docking ui courtesy of JupyterLab's Lumino widgets
+> 4. Schematic visualisation courtesy of d3-hwschematic
+> 5. Testbench simulation with graphical trace output and schematic animation
+> 6. Circuit description as gates, boolean logic or verilog behavioural model
+> 7. Generate arbitrary outputs from truth table and Sum of Products or Karnaugh Map
+
+[from the GitHub page. As of 2021/03/29]
+
# ASIC Timing and Design flow resources
* <https://www.linkedin.com/pulse/asic-design-flow-introduction-timing-constraints-mahmoud-abdellatif/>
* <https://www.icdesigntips.com/2020/10/setup-and-hold-time-explained.html>
* <https://www.vlsiguide.com/2018/07/clock-tree-synthesis-cts.html>
* <https://en.wikipedia.org/wiki/Frequency_divider>
+
+# Geometric Haskell Library
+
+* <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/GeometricAlgebra.hs>
+* <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/PGA.hs>
+* <https://arxiv.org/pdf/1501.06511.pdf>
+* <https://bivector.net/index.html>
+
+# TODO investigate
+
+```
+ https://github.com/idea-fasoc/OpenFASOC
+ https://www.quicklogic.com/2020/06/18/the-tipping-point/
+ https://www.quicklogic.com/blog/
+ https://www.quicklogic.com/2020/09/15/why-open-source-ecosystems-make-good-business-sense/
+ https://www.quicklogic.com/qorc/
+ https://en.wikipedia.org/wiki/RAD750
+ The RAD750 system has a price that is comparable to the RAD6000, the latter of which as of 2002 was listed at US$200,000 (equivalent to $284,292 in 2019).
+ https://theamphour.com/525-open-fpga-toolchains-and-machine-learning-with-brian-faith-of-quicklogic/
+ https://github.blog/2021-03-22-open-innovation-winning-strategy-digital-sovereignty-human-progress/
+ https://github.com/olofk/edalize
+ https://github.com/hdl/containers
+ https://twitter.com/OlofKindgren/status/1374848733746192394
+ You might also want to check out https://umarcor.github.io/osvb/index.html
+ https://www.linkedin.com/pulse/1932021-python-now-replaces-tcl-all-besteda-apis-avidan-efody/
+ “TCL has served us well, over the years, allowing us to provide an API, and at the same time ensure nobody will ever use it. I will miss it”.
+ https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/comb-full-adder.html
+ https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/carry4.html
+ FuseSoC is used by MicroWatt and Western Digital cores
+ OpenTitan also uses FuseSoC
+ LowRISC is UK based
+ https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
+```
projects / libreriscv.git / blobdiff