add pepijn tweet

[libreriscv.git] / resources.mdwn

diff --git a/resources.mdwn b/resources.mdwn
index a647c9bbaf4bbe1f67e7e48376d75dcae665cd77..dc7e66569000845ba0cef7a6a8310d9dd31fad3a 100644 (file)
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -31,6 +31,10 @@ This section is primarily a series of useful links found online
 
 * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
 
+# Energy-efficient cores
+
+* https://arxiv.org/abs/2002.10143
+
 # Communities
 
 * <https://www.reddit.com/r/OpenPOWER/>
@@ -44,7 +48,7 @@ This section is primarily a series of useful links found online
 * https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf 
 * https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf 
 * MALI Midgard
-* Nyuzi
+* [Nyuzi](https://github.com/jbush001/NyuziProcessor)
 * VideoCore IV
 * etnaviv
 
@@ -61,8 +65,13 @@ This section is primarily a series of useful links found online
 
 # D-Cache
 
+- [A Primer on Memory Consistency and Cache Coherence
+](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049)
+
 ## D-Cache Possible Optimizations papers and links
 - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
+- [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of
+Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901)
 
 # BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
 - [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
@@ -211,6 +220,11 @@ see [[conferences]]
 Note: The rest of LIP6's website is in French, but there is a UK flag
 in the corner that gives the English version.
 
+# Logical Equivalence and extraction
+
+* NETGEN
+* CVC https://github.com/d-m-bailey/cvc
+
 # Klayout
 
 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
@@ -309,6 +323,18 @@ Some learning resources I found in the community:
 
 * <https://www.ohwr.org/project/wishbone-gen>
 
+# Bus Architectures
+
+* Avalon <https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf>
+* CXM <https://www.computeexpresslink.org/download-the-specification>
+
+# Vector Processors
+
+* THOR <https://github.com/robfinch/Thor/blob/main/Thor2021/doc/Thor2021.pdf>
+* NEC SX-Aurora
+* RVV
+* MRISC32 <https://github.com/mrisc32/mrisc32>
+
 # LLVM
 
 ## Adding new instructions:
@@ -351,6 +377,7 @@ Some learning resources I found in the community:
 * <https://www.lowrisc.org/open-silicon/>
 * <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
 * <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
+* <https://github.com/ics-jku/wal> - Waveform Analysis
 * <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
   Synchronous Resets? Asynchronous Resets? I am so confused! How will I
   ever know which to use? by Clifford E. Cummings