partially update spike to newer debug spec

[riscv-isa-sim.git] / riscv / execute.cc

diff --git a/riscv/execute.cc b/riscv/execute.cc
index e2e72d69ef244fdd79836b2bbddd60af3017feee..7b42262c589a401a848945e08e77085741b4922b 100644 (file)
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -51,6 +51,11 @@ static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
   return npc;
 }
 
+bool processor_t::slow_path()
+{
+  return debug || state.single_step != state.STEP_NONE || state.dcsr.cause;
+}
+
 // fetch/decode/execute loop
 void processor_t::step(size_t n)
 {
@@ -90,25 +95,28 @@ void processor_t::step(size_t n)
     {
       take_interrupt();
 
-      // When we might single step, use the slow loop instead of the fast one.
-      if (unlikely(debug || state.single_step != state.STEP_NONE || state.dcsr.cause))
+      if (unlikely(slow_path()))
       {
         while (instret < n)
         {
           if (unlikely(state.single_step == state.STEP_STEPPING)) {
             state.single_step = state.STEP_STEPPED;
-          } else if (unlikely(state.single_step == state.STEP_STEPPED)) {
-            state.single_step = state.STEP_NONE;
-            enter_debug_mode(DCSR_CAUSE_STEP);
-            // enter_debug_mode changed state.pc, so we can't just continue.
-            break;
           }
 
           insn_fetch_t fetch = mmu->load_insn(pc);
           if (debug && !state.serialized)
             disasm(fetch.insn);
           pc = execute_insn(this, pc, fetch);
+          bool serialize_before = (pc == PC_SERIALIZE_BEFORE);
+
           advance_pc();
+
+          if (unlikely(state.single_step == state.STEP_STEPPED) && !serialize_before) {
+            state.single_step = state.STEP_NONE;
+            enter_debug_mode(DCSR_CAUSE_STEP);
+            // enter_debug_mode changed state.pc, so we can't just continue.
+            break;
+          }
         }
       }
       else while (instret < n)
@@ -146,6 +154,34 @@ miss:
       take_trap(t, pc);
       n = instret;
     }
+    catch (trigger_matched_t& t)
+    {
+      if (mmu->matched_trigger) {
+        // This exception came from the MMU. That means the instruction hasn't
+        // fully executed yet. We start it again, but this time it won't throw
+        // an exception because matched_trigger is already set. (All memory
+        // instructions are idempotent so restarting is safe.)
+
+        insn_fetch_t fetch = mmu->load_insn(pc);
+        pc = execute_insn(this, pc, fetch);
+        advance_pc();
+
+        delete mmu->matched_trigger;
+        mmu->matched_trigger = NULL;
+      }
+      switch (state.mcontrol[t.index].action) {
+        case ACTION_DEBUG_MODE:
+          enter_debug_mode(DCSR_CAUSE_HWBP);
+          break;
+        case ACTION_DEBUG_EXCEPTION: {
+          mem_trap_t trap(CAUSE_BREAKPOINT, t.address);
+          take_trap(trap, pc);
+          break;
+        }
+        default:
+          abort();
+      }
+    }
 
     state.minstret += instret;
     n -= instret;