[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / c_lt_s.h

diff --git a/riscv/insns/c_lt_s.h b/riscv/insns/c_lt_s.h
index aef73340d7d88530b11f3173c674c939af7a4090..cdb43725474a8b56b3792917a77c7d0d9daf1e18 100644 (file)
--- a/riscv/insns/c_lt_s.h
+++ b/riscv/insns/c_lt_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RC = f32_lt(FRA, FRB);
+RDR = f32_lt(FRS1, FRS2);
 set_fp_exceptions;