[sim,xcc] Changed instruction format to RISC-V

[riscv-isa-sim.git] / riscv / insns / ld.h

diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index 45bbcc2ff19099a347503d8013a13326cfee9932..241af6a1acb19e48bd93bad03d1b3ab5ef847be5 100644 (file)
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,2 @@
 require64;
-RT = mmu.load_int64(RS+SIMM);
+RA = mmu.load_int64(RB+SIMM);