[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / s_s.h

diff --git a/riscv/insns/s_s.h b/riscv/insns/s_s.h
index 837c2585766655008155dd8e2f70a8db668ab0ac..384246ffda7012bc759287d5674c98bf32895369 100644 (file)
--- a/riscv/insns/s_s.h
+++ b/riscv/insns/s_s.h
@@ -1,2 +1,2 @@
 require_fp;
-mmu.store_uint32(RB+SIMM, FRA);
+mmu.store_uint32(RS1+SIMM, FRS2);