[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / sraiw.h

diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h
index 7289347f984d2a173c4f883c201e7be63b3f31c5..0831b1428d00d75caf01b371b02d7c1582b19a6a 100644 (file)
--- a/riscv/insns/sraiw.h
+++ b/riscv/insns/sraiw.h
@@ -1 +1 @@
-RA = sext32(sreg_t(RB) >> SHAMTW);
+RDI = sext32(sreg_t(RS1) >> SHAMTW);