processor_t::processor_t(const char* isa, sim_t* sim, uint32_t id,
bool halt_on_reset)
: debug(false), halt_request(false), sim(sim), ext(NULL), id(id),
- halt_on_reset(halt_on_reset)
+ halt_on_reset(halt_on_reset), last_pc(1), executions(1)
{
parse_isa_string(isa);
register_base_instructions();
lowercase += std::tolower(*r);
const char* p = lowercase.c_str();
- const char* all_subsets = "imafdc";
+ const char* all_subsets = "imafdqc";
max_xlen = 64;
isa = reg_t(2) << 62;
p += 2;
if (!*p) {
- p = all_subsets;
+ p = "imafdc";
} else if (*p == 'g') { // treat "G" as "IMAFD"
tmp = std::string("imafd") + (p+1);
p = &tmp[0];
if (supports_extension('D') && !supports_extension('F'))
bad_isa_string(str);
- // advertise support for supervisor and user modes
- isa |= 1L << ('s' - 'a');
- isa |= 1L << ('u' - 'a');
+ if (supports_extension('Q') && !supports_extension('D'))
+ bad_isa_string(str);
+
+ if (supports_extension('Q') && max_xlen < 64)
+ bad_isa_string(str);
max_isa = isa;
}
reg_t sie = get_field(state.mstatus, MSTATUS_SIE);
reg_t s_enabled = state.prv < PRV_S || (state.prv == PRV_S && sie);
+ // M-ints have highest priority; consider S-ints only if no M-ints pending
if (enabled_interrupts == 0)
enabled_interrupts = pending_interrupts & state.mideleg & -s_enabled;
- if (enabled_interrupts)
+ if (state.dcsr.cause == 0 && enabled_interrupts) {
+ // nonstandard interrupts have highest priority
+ if (enabled_interrupts >> IRQ_M_EXT)
+ enabled_interrupts = enabled_interrupts >> IRQ_M_EXT << IRQ_M_EXT;
+ // external interrupts have next-highest priority
+ else if (enabled_interrupts & (MIP_MEIP | MIP_SEIP))
+ enabled_interrupts = enabled_interrupts & (MIP_MEIP | MIP_SEIP);
+ // software interrupts have next-highest priority
+ else if (enabled_interrupts & (MIP_MSIP | MIP_SSIP))
+ enabled_interrupts = enabled_interrupts & (MIP_MSIP | MIP_SSIP);
+ // timer interrupts have next-highest priority
+ else if (enabled_interrupts & (MIP_MTIP | MIP_STIP))
+ enabled_interrupts = enabled_interrupts & (MIP_MTIP | MIP_STIP);
+ else
+ abort();
+
throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
+ }
}
-void processor_t::set_privilege(reg_t prv)
+static int xlen_to_uxl(int xlen)
+{
+ if (xlen == 32)
+ return 1;
+ if (xlen == 64)
+ return 2;
+ abort();
+}
+
+reg_t processor_t::legalize_privilege(reg_t prv)
{
assert(prv <= PRV_M);
- if (prv == PRV_H)
- prv = PRV_U;
+
+ if (!supports_extension('U'))
+ return PRV_M;
+
+ if (prv == PRV_H || !supports_extension('S'))
+ return PRV_U;
+
+ return prv;
+}
+
+void processor_t::set_privilege(reg_t prv)
+{
mmu->flush_tlb();
- state.prv = prv;
+ state.prv = legalize_privilege(prv);
}
void processor_t::enter_debug_mode(uint8_t cause)
state.dcsr.prv = state.prv;
set_privilege(PRV_M);
state.dpc = state.pc;
- state.pc = debug_rom_entry();
+ state.pc = DEBUG_ROM_ENTRY;
}
void processor_t::take_trap(trap_t& t, reg_t epc)
if (state.dcsr.cause) {
if (t.cause() == CAUSE_BREAKPOINT) {
- state.pc = debug_rom_entry();
+ state.pc = DEBUG_ROM_ENTRY;
} else {
state.pc = DEBUG_ROM_TVEC;
}
if (t.cause() == CAUSE_BREAKPOINT && (
(state.prv == PRV_M && state.dcsr.ebreakm) ||
- (state.prv == PRV_H && state.dcsr.ebreakh) ||
(state.prv == PRV_S && state.dcsr.ebreaks) ||
(state.prv == PRV_U && state.dcsr.ebreaku))) {
enter_debug_mode(DCSR_CAUSE_SWBP);
state.pc = state.stvec;
state.scause = t.cause();
state.sepc = epc;
- if (t.has_badaddr())
- state.sbadaddr = t.get_badaddr();
+ state.sbadaddr = t.get_badaddr();
reg_t s = state.mstatus;
s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
state.pc = (state.mtvec & ~(reg_t)1) + vector;
state.mepc = epc;
state.mcause = t.cause();
- if (t.has_badaddr())
- state.mbadaddr = t.get_badaddr();
+ state.mbadaddr = t.get_badaddr();
reg_t s = state.mstatus;
s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
void processor_t::disasm(insn_t insn)
{
- static uint64_t last_pc = 1, last_bits;
- static uint64_t executions = 1;
-
uint64_t bits = insn.bits() & ((1ULL << (8 * insn_length(insn.bits()))) - 1);
if (last_pc != state.pc || last_bits != bits) {
if (executions != 1) {
mmu->flush_tlb();
reg_t mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE
- | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
- | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
- | MSTATUS_TSR | (ext ? MSTATUS_XS : 0);
+ | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM
+ | MSTATUS_MXR | MSTATUS_TW | MSTATUS_TVM
+ | MSTATUS_TSR | MSTATUS_UXL | MSTATUS_SXL |
+ (ext ? MSTATUS_XS : 0);
+
+ reg_t requested_mpp = legalize_privilege(get_field(val, MSTATUS_MPP));
+ state.mstatus = set_field(state.mstatus, MSTATUS_MPP, requested_mpp);
+ if (supports_extension('S'))
+ mask |= MSTATUS_SPP;
state.mstatus = (state.mstatus & ~mask) | (val & mask);
else
state.mstatus = set_field(state.mstatus, MSTATUS64_SD, dirty);
- // spike supports the notion of xlen < max_xlen, but current priv spec
- // doesn't provide a mechanism to run RV32 software on an RV64 machine
+ state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
+ state.mstatus = set_field(state.mstatus, MSTATUS_UXL, xlen_to_uxl(max_xlen));
+ state.mstatus = set_field(state.mstatus, MSTATUS_SXL, xlen_to_uxl(max_xlen));
+ // U-XLEN == S-XLEN == M-XLEN
xlen = max_xlen;
break;
}
state.mideleg = (state.mideleg & ~delegable_ints) | (val & delegable_ints);
break;
case CSR_MEDELEG: {
- reg_t mask = 0;
-#define DECLARE_CAUSE(name, value) mask |= 1ULL << (value);
-#include "encoding.h"
-#undef DECLARE_CAUSE
+ reg_t mask =
+ (1 << CAUSE_MISALIGNED_FETCH) |
+ (1 << CAUSE_BREAKPOINT) |
+ (1 << CAUSE_USER_ECALL) |
+ (1 << CAUSE_FETCH_PAGE_FAULT) |
+ (1 << CAUSE_LOAD_PAGE_FAULT) |
+ (1 << CAUSE_STORE_PAGE_FAULT);
state.medeleg = (state.medeleg & ~mask) | (val & mask);
break;
}
case CSR_MCOUNTEREN: return state.mcounteren;
case CSR_SSTATUS: {
reg_t mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_SPP | SSTATUS_FS
- | SSTATUS_XS | SSTATUS_SUM;
+ | SSTATUS_XS | SSTATUS_SUM | SSTATUS_UXL;
reg_t sstatus = state.mstatus & mask;
if ((sstatus & SSTATUS_FS) == SSTATUS_FS ||
(sstatus & SSTATUS_XS) == SSTATUS_XS)