#include "decode.h"
#include "config.h"
-#include <cstring>
+#include "devices.h"
+#include <string>
#include <vector>
#include <map>
struct insn_desc_t
{
- uint32_t match;
- uint32_t mask;
+ insn_bits_t match;
+ insn_bits_t mask;
insn_func_t rv32;
insn_func_t rv64;
};
reg_t data;
};
+typedef struct
+{
+ uint8_t prv;
+ bool step;
+ bool ebreakm;
+ bool ebreakh;
+ bool ebreaks;
+ bool ebreaku;
+ bool halt;
+ uint8_t cause;
+} dcsr_t;
+
// architectural state of a RISC-V hart
struct state_t
{
regfile_t<freg_t, NFPR, false> FPR;
// control and status registers
+ reg_t prv;
reg_t mstatus;
reg_t mepc;
reg_t mbadaddr;
- reg_t mtimecmp;
reg_t mscratch;
+ reg_t mtvec;
reg_t mcause;
reg_t minstret;
reg_t mie;
reg_t mip;
+ reg_t medeleg;
+ reg_t mideleg;
+ reg_t mucounteren;
+ reg_t mscounteren;
reg_t sepc;
reg_t sbadaddr;
reg_t sscratch;
reg_t stvec;
reg_t sptbr;
reg_t scause;
- reg_t sutime_delta;
- reg_t suinstret_delta;
- reg_t tohost;
- reg_t fromhost;
+ reg_t dpc;
+ reg_t dscratch;
+ dcsr_t dcsr;
+
uint32_t fflags;
uint32_t frm;
bool serialized; // whether timer CSRs are in a well-defined state
#ifdef RISCV_ENABLE_COMMITLOG
commit_log_reg_t log_reg_write;
+ reg_t last_inst_priv;
#endif
};
// this class represents one processor in a RISC-V machine.
-class processor_t
+class processor_t : public abstract_device_t
{
public:
processor_t(const char* isa, sim_t* sim, uint32_t id);
void set_histogram(bool value);
void reset(bool value);
void step(size_t n); // run for n cycles
- void deliver_ipi(); // register an interprocessor interrupt
bool running() { return run; }
void set_csr(int which, reg_t val);
void raise_interrupt(reg_t which);
state_t* get_state() { return &state; }
extension_t* get_extension() { return ext; }
bool supports_extension(unsigned char ext) {
- return ext >= 'A' && ext <= 'Z' && ((cpuid >> (ext - 'A')) & 1);
+ if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
+ return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
}
- void push_privilege_stack();
- void pop_privilege_stack();
+ void set_privilege(reg_t);
void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
- void update_histogram(size_t pc);
+ void update_histogram(reg_t pc);
void register_insn(insn_desc_t);
void register_extension(extension_t*);
+ // MMIO slave interface
+ bool load(reg_t addr, size_t len, uint8_t* bytes);
+ bool store(reg_t addr, size_t len, const uint8_t* bytes);
+
private:
sim_t* sim;
mmu_t* mmu; // main memory is always accessed via the mmu
extension_t* ext;
disassembler_t* disassembler;
state_t state;
- reg_t cpuid;
uint32_t id;
- int max_xlen;
- int xlen;
+ unsigned max_xlen;
+ unsigned xlen;
+ reg_t isa;
+ std::string isa_string;
bool run; // !reset
+ // When true, display disassembly of each instruction that's executed.
bool debug;
bool histogram_enabled;
std::vector<insn_desc_t> instructions;
- std::vector<insn_desc_t*> opcode_map;
- std::vector<insn_desc_t> opcode_store;
- std::map<size_t,size_t> pc_histogram;
+ std::map<reg_t,uint64_t> pc_histogram;
+
+ static const size_t OPCODE_CACHE_SIZE = 8191;
+ insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];
void check_timer();
void take_interrupt(); // take a trap if any interrupts are pending
void take_trap(trap_t& t, reg_t epc); // take an exception
void disasm(insn_t insn); // disassemble and print an instruction
+ void enter_debug_mode(uint8_t cause);
+
friend class sim_t;
friend class mmu_t;
+ friend class rtc_t;
friend class extension_t;
+ friend class gdbserver_t;
void parse_isa_string(const char* isa);
void build_opcode_map();
+ void register_base_instructions();
insn_func_t decode_insn(insn_t insn);
};