Add debug_module bus device.

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 869873fffe7e9100e336f6229940de36aa6626b5..3511d303e351ab99c987abbe24400bc0bb481a76 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -31,6 +31,18 @@ struct commit_log_reg_t
   reg_t data;
 };
 
+typedef struct
+{
+  uint8_t prv;
+  bool step;
+  bool ebreakm;
+  bool ebreakh;
+  bool ebreaks;
+  bool ebreaku;
+  bool halt;
+  uint8_t cause;
+} dcsr_t;
+
 // architectural state of a RISC-V hart
 struct state_t
 {
@@ -61,6 +73,10 @@ struct state_t
   reg_t stvec;
   reg_t sptbr;
   reg_t scause;
+  reg_t dpc;
+  reg_t dscratch;
+  dcsr_t dcsr;
+
   uint32_t fflags;
   uint32_t frm;
   bool serialized; // whether timer CSRs are in a well-defined state
@@ -73,15 +89,6 @@ struct state_t
 #endif
 };
 
-typedef enum {
-      HR_NONE,
-      HR_STEPPED,       // A single step was completed
-      HR_SWBP,          // sbreak was executed
-      HR_INTERRUPT,     // Execution interrupted by debugger
-      HR_CMDLINE,       // Command line requested that the processor start halted
-      HR_ATTACHED       // Halted because a debugger attached
-} halt_reason_t;
-
 // this class represents one processor in a RISC-V machine.
 class processor_t : public abstract_device_t
 {
@@ -90,8 +97,6 @@ public:
   ~processor_t();
 
   void set_debug(bool value);
-  void set_halted(bool value, halt_reason_t reason);
-  void set_single_step(bool value);
   void set_histogram(bool value);
   void reset(bool value);
   void step(size_t n); // run for n cycles
@@ -131,12 +136,6 @@ private:
   bool run; // !reset
   // When true, display disassembly of each instruction that's executed.
   bool debug;
-  // TODO: Should this just be rolled into `run`?
-  bool halted;  // When true, no instructions are executed.
-  halt_reason_t halt_reason;        // Why is halted true?
-  // When true, execute exactly one instruction (even if halted is true), then
-  // set halted to true and single_step to false.
-  bool single_step;
   bool histogram_enabled;
 
   std::vector<insn_desc_t> instructions;
@@ -150,6 +149,8 @@ private:
   void take_trap(trap_t& t, reg_t epc); // take an exception
   void disasm(insn_t insn); // disassemble and print an instruction
 
+  void enter_debug_mode(uint8_t cause);
+
   friend class sim_t;
   friend class mmu_t;
   friend class rtc_t;