#include <string>
#include <vector>
#include <map>
+#include "debug_rom/debug_rom_defines.h"
class processor_t;
class mmu_t;
struct commit_log_reg_t
{
reg_t addr;
- reg_t data;
+ freg_t data;
};
typedef struct
reg_t mip;
reg_t medeleg;
reg_t mideleg;
- uint32_t mucounteren;
- uint32_t mscounteren;
+ uint32_t mcounteren;
+ uint32_t scounteren;
reg_t sepc;
reg_t sbadaddr;
reg_t sscratch;
reg_t stvec;
- reg_t sptbr;
+ reg_t satp;
reg_t scause;
reg_t dpc;
reg_t dscratch;
#ifdef RISCV_ENABLE_COMMITLOG
commit_log_reg_t log_reg_write;
reg_t last_inst_priv;
+ int last_inst_xlen;
+ int last_inst_flen;
#endif
};
void reset();
void step(size_t n); // run for n cycles
void set_csr(int which, reg_t val);
- void raise_interrupt(reg_t which);
reg_t get_csr(int which);
mmu_t* get_mmu() { return mmu; }
state_t* get_state() { return &state; }
+ unsigned get_xlen() { return xlen; }
+ unsigned get_flen() {
+ return supports_extension('Q') ? 128 :
+ supports_extension('D') ? 64 :
+ supports_extension('F') ? 32 : 0;
+ }
extension_t* get_extension() { return ext; }
bool supports_extension(unsigned char ext) {
if (ext >= 'a' && ext <= 'z') ext += 'A' - 'a';
return ext >= 'A' && ext <= 'Z' && ((isa >> (ext - 'A')) & 1);
}
+ reg_t legalize_privilege(reg_t);
void set_privilege(reg_t);
void yield_load_reservation() { state.load_reservation = (reg_t)-1; }
void update_histogram(reg_t pc);
bool slow_path();
bool halted() { return state.dcsr.cause ? true : false; }
bool halt_request;
- // The unique debug rom address that this hart jumps to when entering debug
- // mode. Rely on the fact that spike hart IDs start at 0 and are consecutive.
- uint32_t debug_rom_entry() {
- return DEBUG_ROM_ENTRY + 4 * id;
- }
// Return the index of a trigger that matched, or -1.
inline int trigger_match(trigger_operation_t operation, reg_t address, reg_t data)
(operation == OPERATION_STORE && !state.mcontrol[i].store) ||
(operation == OPERATION_LOAD && !state.mcontrol[i].load) ||
(state.prv == PRV_M && !state.mcontrol[i].m) ||
- (state.prv == PRV_H && !state.mcontrol[i].h) ||
(state.prv == PRV_S && !state.mcontrol[i].s) ||
(state.prv == PRV_U && !state.mcontrol[i].u)) {
continue;
static const size_t OPCODE_CACHE_SIZE = 8191;
insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];
- void check_timer();
- void take_interrupt(); // take a trap if any interrupts are pending
+ void take_pending_interrupt() { take_interrupt(state.mip & state.mie); }
+ void take_interrupt(reg_t mask); // take first enabled interrupt in mask
void take_trap(trap_t& t, reg_t epc); // take an exception
void disasm(insn_t insn); // disassemble and print an instruction
int paddr_bits();
friend class sim_t;
friend class mmu_t;
- friend class rtc_t;
+ friend class clint_t;
friend class extension_t;
void parse_isa_string(const char* isa);
void build_opcode_map();
void register_base_instructions();
insn_func_t decode_insn(insn_t insn);
+
+ // Track repeated executions for processor_t::disasm()
+ uint64_t last_pc, last_bits, executions;
};
reg_t illegal_instruction(processor_t* p, insn_t insn, reg_t pc);