+get_insn_list = $(shell grep ^DECLARE_INSN $(1) | sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/')
+get_opcode = $(shell grep ^DECLARE_INSN.*\\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
+
riscv_subproject_deps = \
- softfloat_riscv \
softfloat \
-riscv_insn_hdrs := $(notdir $(wildcard $(src_dir)/riscv/insns/*.h))
+riscv_install_prog_srcs = \
riscv_hdrs = \
- applink.h \
common.h \
decode.h \
+ devices.h \
+ disasm.h \
mmu.h \
processor.h \
sim.h \
trap.h \
- opcodes.h \
- insn_header.h \
- insn_footer.h \
- dispatch.h \
-
-NDISPATCH := 10
-DISPATCH_SRCS := \
- dispatch0.cc \
- dispatch1.cc \
- dispatch2.cc \
- dispatch3.cc \
- dispatch4.cc \
- dispatch5.cc \
- dispatch6.cc \
- dispatch7.cc \
- dispatch8.cc \
- dispatch9.cc \
- dispatch10.cc \
-
-$(DISPATCH_SRCS): %.cc: dispatch $(wildcard insns/*.h) $(riscv_hdrs)
- $< $(subst dispatch,,$(subst .cc,,$@)) $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
-
-$(src_dir)/riscv/dispatch.h: %.h: dispatch
- $< $(NDISPATCH) 1024 < $(src_dir)/riscv/opcodes.h > $@
-
-$(patsubst %.h, %.cc, $(riscv_insn_hdrs)): %.cc: insns/%.h $(riscv_hdrs)
- @echo \#define FUNC insn_func_$(@:.cc=) > $@
- @echo \#define OPCODE_MASK MASK_$(@:.cc=) >> $@
- @echo \#define OPCODE_MATCH MATCH_$(@:.cc=) >> $@
- @cat $(src_dir)/riscv/insn_header.h >> $@
- @cat $< >> $@
- @cat $(src_dir)/riscv/insn_footer.h >> $@
+ encoding.h \
+ cachesim.h \
+ memtracer.h \
+ tracer.h \
+ extension.h \
+ rocc.h \
+ insn_template.h \
+ mulhi.h \
+ debug_module.h \
+ remote_bitbang.h \
+ jtag_dtm.h \
+
+riscv_precompiled_hdrs = \
+ insn_template.h \
riscv_srcs = \
- applink.cc \
processor.cc \
+ execute.cc \
sim.cc \
+ interactive.cc \
trap.cc \
- icsim.cc \
+ cachesim.cc \
mmu.cc \
- $(DISPATCH_SRCS) \
+ disasm.cc \
+ extension.cc \
+ extensions.cc \
+ rocc.cc \
+ regnames.cc \
+ devices.cc \
+ rom.cc \
+ clint.cc \
+ debug_module.cc \
+ remote_bitbang.cc \
+ jtag_dtm.cc \
+ $(riscv_gen_srcs) \
riscv_test_srcs =
-riscv_install_prog_srcs = \
- riscv-isa-run.cc \
+riscv_gen_hdrs = \
+ icache.h \
+ insn_list.h \
+
+riscv_insn_list = \
+ add \
+ addi \
+ addiw \
+ addw \
+ amoadd_d \
+ amoadd_w \
+ amoand_d \
+ amoand_w \
+ amomax_d \
+ amomaxu_d \
+ amomaxu_w \
+ amomax_w \
+ amomin_d \
+ amominu_d \
+ amominu_w \
+ amomin_w \
+ amoor_d \
+ amoor_w \
+ amoswap_d \
+ amoswap_w \
+ amoxor_d \
+ amoxor_w \
+ and \
+ andi \
+ auipc \
+ beq \
+ bge \
+ bgeu \
+ blt \
+ bltu \
+ bne \
+ c_add \
+ c_addi4spn \
+ c_addi \
+ c_addw \
+ c_and \
+ c_andi \
+ c_beqz \
+ c_bnez \
+ c_ebreak \
+ c_fld \
+ c_fldsp \
+ c_flw \
+ c_flwsp \
+ c_fsd \
+ c_fsdsp \
+ c_fsw \
+ c_fswsp \
+ c_jal \
+ c_jalr \
+ c_j \
+ c_jr \
+ c_li \
+ c_lui \
+ c_lw \
+ c_lwsp \
+ c_mv \
+ c_or \
+ c_slli \
+ c_srai \
+ c_srli \
+ c_sub \
+ c_subw \
+ c_xor \
+ csrrc \
+ csrrci \
+ csrrs \
+ csrrsi \
+ csrrw \
+ csrrwi \
+ c_sw \
+ c_swsp \
+ div \
+ divu \
+ divuw \
+ divw \
+ dret \
+ ebreak \
+ ecall \
+ fadd_d \
+ fadd_s \
+ fclass_d \
+ fclass_s \
+ fcvt_d_l \
+ fcvt_d_lu \
+ fcvt_d_s \
+ fcvt_d_w \
+ fcvt_d_wu \
+ fcvt_l_d \
+ fcvt_l_s \
+ fcvt_lu_d \
+ fcvt_lu_s \
+ fcvt_s_d \
+ fcvt_s_l \
+ fcvt_s_lu \
+ fcvt_s_w \
+ fcvt_s_wu \
+ fcvt_w_d \
+ fcvt_w_s \
+ fcvt_wu_d \
+ fcvt_wu_s \
+ fdiv_d \
+ fdiv_s \
+ fence \
+ fence_i \
+ feq_d \
+ feq_s \
+ fld \
+ fle_d \
+ fle_s \
+ flt_d \
+ flt_s \
+ flw \
+ fmadd_d \
+ fmadd_s \
+ fmax_d \
+ fmax_s \
+ fmin_d \
+ fmin_s \
+ fmsub_d \
+ fmsub_s \
+ fmul_d \
+ fmul_s \
+ fmv_d_x \
+ fmv_w_x \
+ fmv_x_d \
+ fmv_x_w \
+ fnmadd_d \
+ fnmadd_s \
+ fnmsub_d \
+ fnmsub_s \
+ fsd \
+ fsgnj_d \
+ fsgnjn_d \
+ fsgnjn_s \
+ fsgnj_s \
+ fsgnjx_d \
+ fsgnjx_s \
+ fsqrt_d \
+ fsqrt_s \
+ fsub_d \
+ fsub_s \
+ fsw \
+ jal \
+ jalr \
+ lb \
+ lbu \
+ ld \
+ lh \
+ lhu \
+ lr_d \
+ lr_w \
+ lui \
+ lw \
+ lwu \
+ mret \
+ mul \
+ mulh \
+ mulhsu \
+ mulhu \
+ mulw \
+ or \
+ ori \
+ rem \
+ remu \
+ remuw \
+ remw \
+ sb \
+ sc_d \
+ sc_w \
+ sd \
+ sfence_vma \
+ sh \
+ sll \
+ slli \
+ slliw \
+ sllw \
+ slt \
+ slti \
+ sltiu \
+ sltu \
+ sra \
+ srai \
+ sraiw \
+ sraw \
+ sret \
+ srl \
+ srli \
+ srliw \
+ srlw \
+ sub \
+ subw \
+ sw \
+ wfi \
+ xor \
+ xori \
+
+riscv_gen_srcs = \
+ $(addsuffix .cc,$(riscv_insn_list))
+
+icache_entries := `grep "ICACHE_ENTRIES =" $(src_dir)/riscv/mmu.h | sed 's/.* = \(.*\);/\1/'`
+
+icache.h: mmu.h
+ $(src_dir)/riscv/gen_icache $(icache_entries) > $@.tmp
+ mv $@.tmp $@
+
+insn_list.h: $(src_dir)/riscv/riscv.mk.in
+ for insn in $(foreach insn,$(riscv_insn_list),$(subst .,_,$(insn))) ; do \
+ printf 'DEFINE_INSN(%s)\n' "$${insn}" ; \
+ done > $@.tmp
+ mv $@.tmp $@
+
+$(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc
+ sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/riscv/insn_template.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/riscv/encoding.h,$(subst .cc,,$@))/' > $@
+
+riscv_junk = \
+ $(riscv_gen_srcs) \