sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc,
std::vector<std::pair<reg_t, mem_t*>> mems,
- const std::vector<std::string>& args, std::vector<int> const hartids)
- : htif_t(args), debug_module(this), mems(mems), procs(std::max(nprocs, size_t(1))),
- start_pc(start_pc),
- current_step(0), current_proc(0), debug(false), remote_bitbang(NULL)
+ const std::vector<std::string>& args,
+ std::vector<int> const hartids, unsigned progsize,
+ unsigned max_bus_master_bits)
+ : htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))),
+ start_pc(start_pc), current_step(0), current_proc(0), debug(false),
+ remote_bitbang(NULL), debug_module(this, progsize, max_bus_master_bits)
{
signal(SIGINT, &handle_signal);
0x297, // auipc t0,0x0
0x28593 + (reset_vec_size * 4 << 20), // addi a1, t0, &dtb
0xf1402573, // csrr a0, mhartid
- get_core(0)->xlen == 32 ?
+ get_core(0)->get_xlen() == 32 ?
0x0182a283u : // lw t0,24(t0)
0x0182b283u, // ld t0,24(t0)
0x28067, // jr t0
" reg = <" << i << ">;\n"
" status = \"okay\";\n"
" compatible = \"riscv\";\n"
- " riscv,isa = \"" << procs[i]->isa_string << "\";\n"
- " mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
+ " riscv,isa = \"" << procs[i]->get_isa_string() << "\";\n"
+ " mmu-type = \"riscv," << (procs[i]->get_max_xlen() <= 32 ? "sv32" : "sv48") << "\";\n"
" clock-frequency = <" << CPU_HZ << ">;\n"
" CPU" << i << "_intc: interrupt-controller {\n"
" #interrupt-cells = <1>;\n"
" 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n"
" };\n"
" };\n"
+ " htif {\n"
+ " compatible = \"ucb,htif0\";\n"
+ " };\n"
"};\n";
dts = s.str();