vendor.quicklogic: enable SoC clock configuration

[nmigen.git] / setup.py

diff --git a/setup.py b/setup.py
index d08cddd6c953f9b6751e5403b54187fa341eb4d0..4cd96e793ca25772300f1efc700697c74f682d4a 100644 (file)
--- a/setup.py
+++ b/setup.py
@@ -21,7 +21,9 @@ def doc_version():
         return ""
 
     git = parse_git(".")
-    if git.exact:
+    if not git:
+        return ""
+    elif git.exact:
         return git.format_with("{tag}")
     else:
         return "latest"
@@ -45,10 +47,10 @@ setup(
     ],
     extras_require={
         # this version requirement needs to be synchronized with the one in nmigen.back.verilog!
-        "builtin-yosys": ["nmigen-yosys>=0.9.*"],
+        "builtin-yosys": ["nmigen-yosys>=0.9.post3527.*"],
         "remote-build": ["paramiko~=2.7"],
     },
-    packages=find_packages(exclude=["*.test*"]),
+    packages=find_packages(exclude=["tests*"]),
     entry_points={
         "console_scripts": [
             "nmigen-rpc = nmigen.rpc:main",