#!/usr/bin/env python3
-import sys
from setuptools import setup
from setuptools import find_packages
-if sys.version_info[:3] < (3, 5):
- raise SystemExit("You need Python 3.5+")
-
-
setup(
name="litex",
- version="0.2.dev",
- description="Python tools to design FPGA cores and SoCs",
- long_description=open("README.md").read(),
+ description="Python SoC/Core builder for building FPGA based systems.",
author="Florent Kermarrec",
author_email="florent@enjoy-digital.fr",
url="http://enjoy-digital.fr",
download_url="https://github.com/enjoy-digital/litex",
test_suite="test",
license="BSD",
+ python_requires="~=3.6",
+ install_requires=[
+ "migen",
+ "pyserial",
+ "requests",
+ "pythondata-software-compiler_rt",
+ ],
+ packages=find_packages(exclude=("test*", "sim*", "doc*")),
+ include_package_data=True,
platforms=["Any"],
keywords="HDL ASIC FPGA hardware design",
classifiers=[
"Operating System :: OS Independent",
"Programming Language :: Python",
],
- packages=find_packages(exclude=("test*", "sim*", "doc*")),
- install_requires=["migen", "pyserial"],
- include_package_data=True,
entry_points={
"console_scripts": [
# full names
"litex_term=litex.tools.litex_term:main",
"litex_server=litex.tools.litex_server:main",
+ "litex_jtag_uart=litex.tools.litex_jtag_uart:main",
+ "litex_crossover_uart=litex.tools.litex_crossover_uart:main",
"litex_sim=litex.tools.litex_sim:main",
"litex_read_verilog=litex.tools.litex_read_verilog:main",
"litex_simple=litex.boards.targets.simple:main",
+ "litex_json2dts=litex.tools.litex_json2dts:main",
# short names
"lxterm=litex.tools.litex_term:main",
"lxserver=litex.tools.litex_server:main",