add link to kestrel nmigen cpu

[libreriscv.git] / shakti / m_class / AXI.mdwn

diff --git a/shakti/m_class/AXI.mdwn b/shakti/m_class/AXI.mdwn
index 61beb10e399ddd5a68f06b7d03ab62be360b36da..d6eecca39deb78e6c1ff6eb1138d2b9ab2fddcbf 100644 (file)
--- a/shakti/m_class/AXI.mdwn
+++ b/shakti/m_class/AXI.mdwn
@@ -6,6 +6,8 @@ See also [[wishbone]] Bus
 * <https://github.com/alexforencich/verilog-axis>
 * <https://github.com/qermit/WishboneAXI/tree/master/cores/Wishbone2AXI/hdl>
 
-# AXI4 in nmigen
+# AXI4 in migen
+
+Implementations of AXI4 in nmigen (not just bridges)
 
 * <https://github.com/peteut/migen-axi>