+# EINT
+
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=14>
+* <https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/>
+ includes GPIO, SPI, UART, JTAG, I2C, PinCtrl, UART and PWM. Also included
+ is a Watchdog Timer and others.
+* <https://opencores.org/project,simple_pic>