update image with correct mux

[libreriscv.git] / shakti / m_class / EINT.mdwn

diff --git a/shakti/m_class/EINT.mdwn b/shakti/m_class/EINT.mdwn
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..054cfb0990e3f7ae9e99aa1b3db15c41dc802141 100644 (file)
--- a/shakti/m_class/EINT.mdwn
+++ b/shakti/m_class/EINT.mdwn
@@ -0,0 +1,13 @@
+# EINT
+
+aka "PLIC"
+
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=14>
+* <https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/>
+  includes GPIO, SPI, UART, JTAG, I2C, PinCtrl, UART and PWM.  Also included
+  is a Watchdog Timer and others.
+* <https://opencores.org/project,simple_pic>
+* <https://bitbucket.org/casl/c-class/src/0e77398a030bfd705930d0f1b8b9b5050d76e265/src/peripherals/plic/?at=master>
+* <https://github.com/RoaLogic/plic>
+* <https://github.com/pulp-platform/ariane/tree/master/src/plic>
+* <https://github.com/lowRISC/rv_plic>