add spi interface page

[libreriscv.git] / shakti / m_class / SPI.mdwn

diff --git a/shakti/m_class/SPI.mdwn b/shakti/m_class/SPI.mdwn
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+# SPI
+
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=6>
+* Optional 4-wire SPI NAND/NOR for boot (XIP - Execute In-place - recommended).
+* <https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/>
+  includes GPIO, SPI, UART, JTAG, I2C, PinCtrl, UART and PWM.  Also included
+  is a Watchdog Timer and others.
+* APB to SPI <https://opencores.org/project,apb2spi>
+* ASIC-proven <https://opencores.org/project,spi_master_slave>
+* Wishbone-compliant <https://opencores.org/project,simple_spi>
+