(no commit message)

[libreriscv.git] / shakti / m_class / SPI.mdwn

diff --git a/shakti/m_class/SPI.mdwn b/shakti/m_class/SPI.mdwn
index f9d82cf98a20c5580e8e37e7b1290f9851bd0160..cb56f22a85eaec9437757686f6d998da68681d12 100644 (file)
--- a/shakti/m_class/SPI.mdwn
+++ b/shakti/m_class/SPI.mdwn
@@ -1,5 +1,7 @@
 # SPI
 
+see also [[QSPI]]
+
 * <http://bugs.libre-riscv.org/show_bug.cgi?id=6>
 * Optional 4-wire SPI NAND/NOR for boot (XIP - Execute In-place - recommended).
 * <https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/>
@@ -7,5 +9,8 @@
   is a Watchdog Timer and others.
 * APB to SPI <https://opencores.org/project,apb2spi>
 * ASIC-proven <https://opencores.org/project,spi_master_slave>
+https://opencores.org/websvn/filedetails?repname=spi_master_slave&path=%2Fspi_master_slave%2Ftrunk%2Frtl%2Fspi_master_slave%2Fspi_master.vhd
 * Wishbone-compliant <https://opencores.org/project,simple_spi>
-
+* Raptor Engineering litespi, improved <
+https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litespi>
+* Also Shakti E-Class peripheral set in BSV