Add verilog implementation of displayport

[libreriscv.git] / shakti / m_class / ULPI.mdwn

diff --git a/shakti/m_class/ULPI.mdwn b/shakti/m_class/ULPI.mdwn
index 25f20848e7b1a026cbeb66bec8b921966b7d10c0..6e9d7bf2d4d7ffdc25362ffdbe1729ae2cd4cc9e 100644 (file)
--- a/shakti/m_class/ULPI.mdwn
+++ b/shakti/m_class/ULPI.mdwn
@@ -1,8 +1,29 @@
 # USB2 (ULPI)
 
+## Requirements
+* PHY (to be determined)
+* DDR mode
+* ...
+
+## LICENSE
+BSD I guess...(fix me)
+
+## Useful resources
+
+![UTMI_interface](https://www.crifan.com/files/pic/serial_story/other_site/p_blog_bb.JPG)
+
+![UTMI+levels](https://www.crifan.com/files/pic/serial_story/other_site/p_blog_aa.JPG)
+
+![UTMI+level3_interface](https://www.crifan.com/files/pic/serial_story/other_site/p_blog_cc.JPG)
+
+![LPI_signals](https://www.crifan.com/files/pic/serial_story/other_site/p_blog_dd.JPG)
+
+![LPI_signals_table](https://www.crifan.com/files/pic/serial_story/other_site/p_blog_dd.JPG)
+
+## reference
 * <https://opencores.org/project,ulpi_wrapper> (GPL'd)
 * <https://github.com/mossmann/daisho/blob/master/sw/fpga/common/usb3/usb2_ulpi.v> (BSD)
 * <https://opencores.org/project,usb>
 * <https://github.com/alexforencich/verilog-wishbone>
-
+* <https://github.com/www-asics-ws/usb2_dev>