(no commit message)

[libreriscv.git] / shakti / m_class / pinmux.mdwn

diff --git a/shakti/m_class/pinmux.mdwn b/shakti/m_class/pinmux.mdwn
index 2243e40b398b8a554d5d22222f752be8e44acfe1..34178ce4e9b9ee36f6d52e5806f0bac5010d4c2f 100644 (file)
--- a/shakti/m_class/pinmux.mdwn
+++ b/shakti/m_class/pinmux.mdwn
@@ -7,7 +7,7 @@
 * <https://github.com/sifive/freedom/blob/master/src/main/scala/everywhere/e300artydevkit/Platform.scala>
   Pinmux ("IOF") for multiplexing several I/O functions onto a single pin
 
-Complex!  
+Surprisingly complex!  
 
 # Requirements
 
@@ -18,16 +18,34 @@ optional pull-up and pull-down resistors, in an IDENTICAL fashion to
 that of ALL major well-known embedded SoCs from ST Micro, Cypress,
 Texas Instruments, NXP, Rockchip, Allwinner and many many others".
 
+* Number of wires shall be minimised especially in cases where
+  the IO pad (puen, oe) need to change under the control of the
+  function (not the GPIO registers).
+* There shall be no short-circuits created by multiple input
+  pins trying to drive the same input function
+* The IO pad shall have pull-up enable, pull-down enable, variable
+  frequency de-bounce, tri-state capability, Open Drain and CMOS
+  Push-Push.
+* The amount of latency (gates in between I/O pad and function)
+  shall be minimised
+
 ## Analysis
 
 Questions:
 
-* Can damage occur by outputs being short-circuited to outputs in any way?
+* Can damage occur (to the ASIC) by outputs being short-circuited to outputs
+  in any way?
   A partial analysis showed that because outputs are one-to-many, there should
   not be a possibility for that to occur.  However what if a function is
   bi-directional?
 * Is de-bouncing always needed on every input?  Is it ok for de-bouncing
   to be only done on EINT?
+* Can the input mux be turned round and "selector" logic added so that
+  there is no possibility of damage to inputs?
+
+# Images
+
+* [[mygpiomux.jpg]]
 
 # GSoC2018
 
@@ -39,12 +57,31 @@ Introductions:
   lots of different stuff.  Guardian of the EOMA68 Certification Mark,
   and currently responsible for coordinating the design of a fully Libre
   RISC-V SoC in collaboration with the RISE Group, IIT Madras, Shakti Project.
+  not much experience at verilog (have done a couple of tutorials).
+* Xing GUO(xing) - undergraduate (3rd year) from Southeast
+  University, EE student, C/C++, Python, Verilog, assembly (not very proficient), 
+  Haskell (not very proficient). RTL design, server maintenance.
+  E-mail: higuoxing at gmail dot com, Github: [Higuoxing](https://github.com/higuoxing) some of my projects are there :)
+* Aurojyoti Das(auro) - graduate student (MSc Electrical - Microelectronics) 
+  at TU Delft, Netherlands. C/C++, Verilog, VHDL, SystemVerilog, RTL Design, 
+  Logic Verification, Python/Perl/Shell scripting, Analog IC Design (currently learning) 
+  
+Hardware available:
+
+* lkcl: ZC706
+* xing: zynq-7020 and Xilinx XC7A100T-484
 
 # Discussion and Links
 
+* <https://elinux.org/images/b/b6/Pin_Control_Subsystem_Overview.pdf>
 * <https://lists.librecores.org/pipermail/discussion/2018-February/thread.html>
 * <https://lists.librecores.org/pipermail/discussion/2018-January/000404.html>
 
+## Some Useful Resource
+
+* <https://docs.scala-lang.org/tour/tour-of-scala.html> A brief Scala tutorial
+* <https://github.com/ucb-bar/chisel-tutorial> A brief Chisel tutorial
+
 # Pinouts Specification
 
 Covered in [[pinouts]].  The general idea is to target several