(no commit message)

[libreriscv.git] / shakti / m_class / pinmux.mdwn

diff --git a/shakti/m_class/pinmux.mdwn b/shakti/m_class/pinmux.mdwn
index 58752bb61aad425760391c3fe64fd11424468791..fdf7fed2190bfeaf385b548cb766b553d44d6f96 100644 (file)
--- a/shakti/m_class/pinmux.mdwn
+++ b/shakti/m_class/pinmux.mdwn
@@ -63,10 +63,6 @@ Introductions:
   and currently responsible for coordinating the design of a fully Libre
   RISC-V SoC in collaboration with the RISE Group, IIT Madras, Shakti Project.
   not much experience at verilog (have done a couple of tutorials).
-* Xing GUO(xing) - undergraduate (3rd year) from Southeast
-  University, EE student, C/C++, Python, Verilog, assembly (not very proficient), 
-  Haskell (not very proficient). RTL design, server maintenance.
-  E-mail: higuoxing at gmail dot com, Github: [Higuoxing](https://github.com/higuoxing) some of my projects are there :)
 * Aurojyoti Das(auro) - graduate student (MSc Electrical - Microelectronics) 
   at TU Delft, Netherlands. C/C++, Verilog, VHDL, SystemVerilog, RTL Design, 
   Logic Verification, Python/Perl/Shell scripting, Analog IC Design (currently learning) 
@@ -74,7 +70,7 @@ Introductions:
 Hardware available:
 
 * lkcl: ZC706
-* xing: zynq-7020 and Xilinx XC7A100T-484
+* xing: zynq-7020 and Xilinx XC7A100T-484 if needed contact him! <higuoxing@gmail.com>
 
 # Discussion and Links
 
@@ -89,6 +85,7 @@ Hardware available:
 * <https://github.com/xfguo/tbgen/blob/master/tbgen.py> auto-generated test module for verilog
 * <https://github.com/kdurant/verilog-testbench> described here <https://www.vim.org/scripts/script.php?script_id=4596>
 * <http://agilesoc.com/open-source-projects/svunit/> - SVunit - unit testing for verilog
+* [FPGA Overview](http://www.springer.com/cda/content/document/cda_downloaddocument/9781461435938-c2.pdf?SGWID=0-0-45-1333135-p174308376) Useful in writing GPIO related codes...
 
 # Pinouts Specification