is a Watchdog Timer and others.
* <https://github.com/sifive/freedom/blob/master/src/main/scala/everywhere/e300artydevkit/Platform.scala>
Pinmux ("IOF") for multiplexing several I/O functions onto a single pin
+* <https://bitbucket.org/casl/pinmux.git> - implementation by Shakti RISE Group
Surprisingly complex!
that of ALL major well-known embedded SoCs from ST Micro, Cypress,
Texas Instruments, NXP, Rockchip, Allwinner and many many others".
+* The IO pad shall have pull-up enable, pull-down enable, variable
+ frequency de-bounce (schmidt trigger), tri-state capability,
+ variable current drive (on input), Open Drain and CMOS Push-Push.
+* Certain functions shall have the ability to control whether
+ IO pads will be input or output (not the GPIO registers).
+* Number of wires shall be minimised especially in cases where
+ the IO pad (puen, oe) need to change under the control of the
+ function (not the GPIO registers).
+* The amount of latency (gates in between I/O pad and function)
+ shall be minimised
+* There shall be no short-circuits created by multiple input
+ pins trying to drive the same input function
+* There shall be no short-circuits even when functions control
+ when the IO pad is an input.
+
## Analysis
Questions:
# Images
-* [[mygpiomux.jpg]
+* [[mygpiomux.jpg]]
# GSoC2018
and currently responsible for coordinating the design of a fully Libre
RISC-V SoC in collaboration with the RISE Group, IIT Madras, Shakti Project.
not much experience at verilog (have done a couple of tutorials).
-* Xing GUO(xing) - undergraduate (3rd year) from Southeast
- University, EE student, C/C++, Python, Verilog, assembly (not very proficient),
- Haskell (not very proficient). RTL design, server maintenance.
- E-mail: higuoxing at gmail dot com, Github: [Higuoxing](https://github.com/higuoxing) some of my projects are there :)
* Aurojyoti Das(auro) - graduate student (MSc Electrical - Microelectronics)
at TU Delft, Netherlands. C/C++, Verilog, VHDL, SystemVerilog, RTL Design,
Logic Verification, Python/Perl/Shell scripting, Analog IC Design (currently learning)
Hardware available:
* lkcl: ZC706
-* xing: zynq-7020 and Xilinx XC7A100T-484
+* xing: zynq-7020 and Xilinx XC7A100T-484 if needed contact him! <higuoxing@gmail.com>
# Discussion and Links
* <https://lists.librecores.org/pipermail/discussion/2018-February/thread.html>
* <https://lists.librecores.org/pipermail/discussion/2018-January/000404.html>
+# Some Useful Resource
+* <https://github.com/ucb-bar/generator-bootcamp> Interactive tutorial on Scala and Chisel (best one, take it, trust me!)
+* <https://docs.scala-lang.org/tour/tour-of-scala.html> A brief Scala tutorial
+* <https://github.com/ucb-bar/chisel-tutorial> A brief Chisel tutorial
+* <https://github.com/xfguo/tbgen/blob/master/tbgen.py> auto-generated test module for verilog
+* <https://github.com/kdurant/verilog-testbench> described here <https://www.vim.org/scripts/script.php?script_id=4596>
+* <http://agilesoc.com/open-source-projects/svunit/> - SVunit - unit testing for verilog
+* [FPGA Overview](http://www.springer.com/cda/content/document/cda_downloaddocument/9781461435938-c2.pdf?SGWID=0-0-45-1333135-p174308376) Useful in writing GPIO related codes...
+
# Pinouts Specification
Covered in [[pinouts]]. The general idea is to target several