add slides

[libreriscv.git] / shakti / m_class / wishbone.mdwn

diff --git a/shakti/m_class/wishbone.mdwn b/shakti/m_class/wishbone.mdwn
index 6748b9f8e4b0136dee8ca538d82366fbea9346b5..2434f3ef6c435b90400e2ac26588bac139f647e9 100644 (file)
--- a/shakti/m_class/wishbone.mdwn
+++ b/shakti/m_class/wishbone.mdwn
@@ -4,4 +4,4 @@ See also [[AXI]] Bus
 
 * <http://bugs.libre-riscv.org/show_bug.cgi?id=11>
 * <https://github.com/alexforencich/verilog-wishbone>
-* <https://github.com/albertxie/iverilog-tutorial.git>
+* <https://github.com/qermit/WishboneAXI>