whoops

[libreriscv.git] / shakti / m_class / wishbone.mdwn

diff --git a/shakti/m_class/wishbone.mdwn b/shakti/m_class/wishbone.mdwn
index e623b71fd6ae5218ae574c13dead90a659d8a3af..6b43b21aad4790c3fe48ebbbeee3e7e612cabcc1 100644 (file)
--- a/shakti/m_class/wishbone.mdwn
+++ b/shakti/m_class/wishbone.mdwn
@@ -1,5 +1,11 @@
 # Wishbone Bridge
 
 See also [[AXI]] Bus
+
 * <http://bugs.libre-riscv.org/show_bug.cgi?id=11>
 * <https://github.com/alexforencich/verilog-wishbone>
+* <https://github.com/qermit/WishboneAXI>
+* <https://github.com/bluecmd/wb-axi>
+* <https://github.com/m-labs/nmigen-soc>
+* <https://opencores.org/projects/wrimm>
+