details see
<http://processors.wiki.ti.com/index.php/General_hardware_design/BGA_PCB_design>
+[[shakti_libre_riscv.jpg]]
+
## Targetting full Libre Licensing to the bedrock.
The only barrier to being able to replicate the masks from scratch
* SD/MMC for on-PCB eMMC (care needed on power/boot sequence)
* NAND Flash (not recommended), requires 8080/ATI-style Bus with dedicated CS#
* Optional 4-wire SPI NAND/NOR for boot (XIP - Execute In-place - recommended).
-* Audio over I2S (5-pin: 4 for output, 1 for input), fall-back to USB Audio
+* Audio over [[I2S]] (5-pin: 4 for output, 1 for input), fall-back to USB Audio
+* Audio also over [[AC97]]
* Some additional SPI peripherals, e.g. connection to low-power MCU.
* GPIO (EINT-capable, with wakeup) for buttons, power, volume etc.
* Camera(s) either by CSI-1 (parallel CSI) or better by USB
# Proposed Interfaces
+* Plain [[GPIO]] multiplexed with a [[pinmux]] onto (nearly) all other pins
* RGB/TTL up to 1440x900 @ 60fps, 24-bit colour
* 2x 1-lane SPI
* 1x 4-lane (quad) SPI
* 3x UART (TX/RX only)
* 3x [[I2C]] (in case of address clashes between peripherals)
* 8080-style AT/XT/ATI MCU Bus Interface, with multiple (8x CS#) lines
-* 3x PWM-capable GPIO
-* 32x EINT-cable GPIO with full edge-triggered and low/high IRQ capability
+* 3x [[PWM]]-capable GPIO
+* 32x [[EINT]]-cable GPIO with full edge-triggered and low/high IRQ capability
* 1x [[I2S]] audio with 4-wire output and 1-wire input.
* 3x USB2 (ULPI for reduced pincount) each capable of USB-OTG support
* DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
Some interfaces at:
+* <https://github.com/RoaLogic/apb4_gpio>
* <https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/>
includes GPIO, SPI, UART, JTAG, I2C, PinCtrl, UART and PWM. Also included
is a Watchdog Timer and others.
* <https://github.com/sifive/freedom/blob/master/src/main/scala/everywhere/e300artydevkit/Platform.scala>
Pinmux ("IOF") for multiplexing several I/O functions onto a single pin
+* <https://bitbucket.org/casl/c-class/src/0e77398a030bfd705930d0f1b8b9b5050d76e265/src/peripherals/?at=master>
+ including AXI, DMA, GPIO, I2C, JTAG, PLIC, QSPI, SDRAM, UART (and TCM?). FlexBus, HyperBus and xSPI to
+ be added.
List of Interfaces:
* [[I2C]]
* [[I2S]]
+* [[PWM]]
+* [[EINT]]
* [[FlexBus]]
* LCD / RGB/TTL [[RGBTTL]]
* [[SPI]]
* SD/MMC and eMMC [[sdmmc]]
* Pin Multiplexing [[pinmux]]
+* Gigabit Ethernet [[RGMII]]
+
+List of Internal Interfaces:
+
+* [[AXI]]
+* [[wishbone]]
# Items requiring clarification, or proposals TBD