testsuite/common/alu-tst$(EXEEXT)
@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_8 = aarch64/libsim.a
@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_9 = aarch64/run
-@SIM_ENABLE_ARCH_arm_TRUE@am__append_10 = arm/run
-@SIM_ENABLE_ARCH_avr_TRUE@am__append_11 = avr/run
-@SIM_ENABLE_ARCH_bfin_TRUE@am__append_12 = bfin/run
-@SIM_ENABLE_ARCH_bfin_TRUE@am__append_13 = bfin_SIM_EXTRA_HW_DEVICES="$(bfin_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_bpf_TRUE@am__append_14 = bpf/run
-@SIM_ENABLE_ARCH_bpf_TRUE@am__append_15 = \
+@SIM_ENABLE_ARCH_arm_TRUE@am__append_10 = arm/libsim.a
+@SIM_ENABLE_ARCH_arm_TRUE@am__append_11 = arm/run
+@SIM_ENABLE_ARCH_avr_TRUE@am__append_12 = avr/libsim.a
+@SIM_ENABLE_ARCH_avr_TRUE@am__append_13 = avr/run
+@SIM_ENABLE_ARCH_bfin_TRUE@am__append_14 = bfin/libsim.a
+@SIM_ENABLE_ARCH_bfin_TRUE@am__append_15 = bfin/run
+@SIM_ENABLE_ARCH_bfin_TRUE@am__append_16 = bfin_SIM_EXTRA_HW_DEVICES="$(bfin_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_bpf_TRUE@am__append_17 = bpf/libsim.a
+@SIM_ENABLE_ARCH_bpf_TRUE@am__append_18 = bpf/run
+@SIM_ENABLE_ARCH_bpf_TRUE@am__append_19 = \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/eng-le.h \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/eng-be.h
-@SIM_ENABLE_ARCH_bpf_TRUE@am__append_16 = $(bpf_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_bpf_TRUE@am__append_17 = $(bpf_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_18 = cr16/run
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_19 = cr16/simops.h
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_20 = $(cr16_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_21 = cr16/gencode
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_22 = $(cr16_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_23 = cris/run
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_24 = cris_SIM_EXTRA_HW_DEVICES="$(cris_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_25 = cris/rvdummy
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_26 = \
+@SIM_ENABLE_ARCH_bpf_TRUE@am__append_20 = $(bpf_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_bpf_TRUE@am__append_21 = $(bpf_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_22 = cr16/libsim.a
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_23 = cr16/run
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_24 = cr16/simops.h
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_25 = $(cr16_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_26 = cr16/gencode
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_27 = $(cr16_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_28 = cris/libsim.a
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_29 = cris/run
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_30 = cris_SIM_EXTRA_HW_DEVICES="$(cris_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_31 = cris/rvdummy
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_32 = \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/engv10.h \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/engv32.h
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_27 = $(cris_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_28 = $(cris_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_29 = d10v/run
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_30 = d10v/simops.h
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_31 = $(d10v_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_32 = d10v/gencode
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_33 = $(d10v_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_erc32_TRUE@am__append_34 = erc32/run erc32/sis
-@SIM_ENABLE_ARCH_erc32_TRUE@am__append_35 = sim-%D-install-exec-local
-@SIM_ENABLE_ARCH_erc32_TRUE@am__append_36 = sim-erc32-uninstall-local
-@SIM_ENABLE_ARCH_examples_TRUE@am__append_37 = example-synacor/run
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_38 = frv/run
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_39 = frv/eng.h
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_40 = $(frv_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_41 = $(frv_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_ft32_TRUE@am__append_42 = ft32/run
-@SIM_ENABLE_ARCH_h8300_TRUE@am__append_43 = h8300/run
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_44 = iq2000/run
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_45 = iq2000/eng.h
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_46 = $(iq2000_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_47 = $(iq2000_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_48 = lm32/run
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_49 = lm32_SIM_EXTRA_HW_DEVICES="$(lm32_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_50 = lm32/eng.h
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_51 = $(lm32_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_52 = $(lm32_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_53 = m32c/run
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_54 = $(m32c_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_55 = m32c/opc2c
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_56 = \
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_33 = $(cris_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_34 = $(cris_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_35 = d10v/libsim.a
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_36 = d10v/run
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_37 = d10v/simops.h
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_38 = $(d10v_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_39 = d10v/gencode
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_40 = $(d10v_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_erc32_TRUE@am__append_41 = erc32/libsim.a
+@SIM_ENABLE_ARCH_erc32_TRUE@am__append_42 = erc32/run erc32/sis
+@SIM_ENABLE_ARCH_erc32_TRUE@am__append_43 = sim-%D-install-exec-local
+@SIM_ENABLE_ARCH_erc32_TRUE@am__append_44 = sim-erc32-uninstall-local
+@SIM_ENABLE_ARCH_examples_TRUE@am__append_45 = example-synacor/libsim.a
+@SIM_ENABLE_ARCH_examples_TRUE@am__append_46 = example-synacor/run
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_47 = frv/libsim.a
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_48 = frv/run
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_49 = frv/eng.h
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_50 = $(frv_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_51 = $(frv_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_ft32_TRUE@am__append_52 = ft32/libsim.a
+@SIM_ENABLE_ARCH_ft32_TRUE@am__append_53 = ft32/run
+@SIM_ENABLE_ARCH_h8300_TRUE@am__append_54 = h8300/libsim.a
+@SIM_ENABLE_ARCH_h8300_TRUE@am__append_55 = h8300/run
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_56 = iq2000/libsim.a
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_57 = iq2000/run
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_58 = iq2000/eng.h
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_59 = $(iq2000_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_60 = $(iq2000_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_61 = lm32/libsim.a
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_62 = lm32/run
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_63 = lm32_SIM_EXTRA_HW_DEVICES="$(lm32_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_64 = lm32/eng.h
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_65 = $(lm32_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_66 = $(lm32_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_67 = m32c/libsim.a
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_68 = m32c/run
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_69 = $(m32c_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_70 = m32c/opc2c
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_71 = \
@SIM_ENABLE_ARCH_m32c_TRUE@ $(m32c_BUILD_OUTPUTS) \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c.log \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.c.log
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_57 = m32r/run
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_58 = m32r_SIM_EXTRA_HW_DEVICES="$(m32r_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_59 = \
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_72 = m32r/libsim.a
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_73 = m32r/run
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_74 = m32r_SIM_EXTRA_HW_DEVICES="$(m32r_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_75 = \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng.h \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/engx.h \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng2.h
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_60 = $(m32r_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_61 = $(m32r_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_62 = m68hc11/run
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_63 = m68hc11_SIM_EXTRA_HW_DEVICES="$(m68hc11_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_64 = $(m68hc11_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_65 = m68hc11/gencode
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_66 = $(m68hc11_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mcore_TRUE@am__append_67 = mcore/run
-@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_68 = microblaze/run
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_69 = mips/run
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_70 = mips_SIM_EXTRA_HW_DEVICES="$(mips_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_71 = mips/itable.h \
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_76 = $(m32r_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_77 = $(m32r_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_78 = m68hc11/libsim.a
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_79 = m68hc11/run
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_80 = m68hc11_SIM_EXTRA_HW_DEVICES="$(m68hc11_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_81 = $(m68hc11_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_82 = m68hc11/gencode
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_83 = $(m68hc11_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mcore_TRUE@am__append_84 = mcore/libsim.a
+@SIM_ENABLE_ARCH_mcore_TRUE@am__append_85 = mcore/run
+@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_86 = microblaze/libsim.a
+@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_87 = microblaze/run
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_88 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/support.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/itable.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/semantics.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/idecode.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/icache.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/engine.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/irun.o
+
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_89 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_support.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_semantics.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_idecode.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_icache.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m32_support.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m32_semantics.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m32_idecode.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m32_icache.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/itable.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16run.o
+
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_90 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI_OBJ) \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o
+
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_91 = mips/libsim.a
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_92 = mips/run
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_93 = mips_SIM_EXTRA_HW_DEVICES="$(mips_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_94 = mips/itable.h \
@SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_MULTI_SRC)
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_72 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_95 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/stamp-gen-mode-single
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_73 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_96 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mode-m16-m16 \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mode-m16-m32
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_74 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_97 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI_SRC) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-igen \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-run
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_75 = $(mips_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_76 = $(mips_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_77 = mips/multi-include.h mips/multi-run.c
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_78 = mn10300/run
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_79 = mn10300_SIM_EXTRA_HW_DEVICES="$(mn10300_SIM_EXTRA_HW_DEVICES)"
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_80 = \
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_98 = $(mips_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_99 = $(mips_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_100 = mips/multi-include.h mips/multi-run.c
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_101 = mn10300/libsim.a
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_102 = mn10300/run
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_103 = mn10300_SIM_EXTRA_HW_DEVICES="$(mn10300_SIM_EXTRA_HW_DEVICES)"
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_104 = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_81 = $(mn10300_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_82 = $(mn10300_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_moxie_TRUE@am__append_83 = moxie/run
-@SIM_ENABLE_ARCH_msp430_TRUE@am__append_84 = msp430/run
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_85 = or1k/run
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_86 = or1k/eng.h
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_87 = $(or1k_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_88 = $(or1k_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_89 = ppc/run ppc/psim
-@SIM_ENABLE_ARCH_pru_TRUE@am__append_90 = pru/run
-@SIM_ENABLE_ARCH_riscv_TRUE@am__append_91 = riscv/run
-@SIM_ENABLE_ARCH_rl78_TRUE@am__append_92 = rl78/run
-@SIM_ENABLE_ARCH_rx_TRUE@am__append_93 = rx/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_94 = sh/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_95 = \
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_105 = $(mn10300_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_106 = $(mn10300_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_moxie_TRUE@am__append_107 = moxie/run
+@SIM_ENABLE_ARCH_msp430_TRUE@am__append_108 = msp430/run
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_109 = or1k/run
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_110 = or1k/eng.h
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_111 = $(or1k_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_112 = $(or1k_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_113 = ppc/run ppc/psim
+@SIM_ENABLE_ARCH_pru_TRUE@am__append_114 = pru/run
+@SIM_ENABLE_ARCH_riscv_TRUE@am__append_115 = riscv/run
+@SIM_ENABLE_ARCH_rl78_TRUE@am__append_116 = rl78/run
+@SIM_ENABLE_ARCH_rx_TRUE@am__append_117 = rx/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_118 = sh/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_119 = \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_96 = $(sh_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_97 = sh/gencode
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_98 = $(sh_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_99 = v850/run
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_100 = \
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_120 = $(sh_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_121 = sh/gencode
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_122 = $(sh_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_123 = v850/run
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_124 = \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_101 = $(v850_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_102 = $(v850_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_125 = $(v850_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_126 = $(v850_BUILD_OUTPUTS)
subdir = .
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
am_aarch64_libsim_a_OBJECTS =
aarch64_libsim_a_OBJECTS = $(am_aarch64_libsim_a_OBJECTS)
am__dirstamp = $(am__leading_dot)dirstamp
+arm_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_DEPENDENCIES = arm/wrapper.o \
+@SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_arm_TRUE@ %,arm/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_arm_TRUE@ %,arm/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_arm_TRUE@ arm/armemu.o arm/armemu32.o \
+@SIM_ENABLE_ARCH_arm_TRUE@ arm/arminit.o arm/armos.o \
+@SIM_ENABLE_ARCH_arm_TRUE@ arm/armsupp.o arm/armvirt.o \
+@SIM_ENABLE_ARCH_arm_TRUE@ arm/thumbemu.o arm/armcopro.o \
+@SIM_ENABLE_ARCH_arm_TRUE@ arm/maverick.o arm/iwmmxt.o \
+@SIM_ENABLE_ARCH_arm_TRUE@ arm/modules.o
+am_arm_libsim_a_OBJECTS =
+arm_libsim_a_OBJECTS = $(am_arm_libsim_a_OBJECTS)
+avr_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_DEPENDENCIES = avr/interp.o \
+@SIM_ENABLE_ARCH_avr_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_avr_TRUE@ %,avr/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_avr_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_avr_TRUE@ %,avr/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_avr_TRUE@ avr/modules.o avr/sim-resume.o
+am_avr_libsim_a_OBJECTS =
+avr_libsim_a_OBJECTS = $(am_avr_libsim_a_OBJECTS)
+bfin_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_bfin_TRUE@bfin_libsim_a_DEPENDENCIES = $(patsubst \
+@SIM_ENABLE_ARCH_bfin_TRUE@ %,bfin/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_bfin_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_bfin_TRUE@ %,bfin/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_bfin_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_bfin_TRUE@ %,bfin/dv-%.o,$(bfin_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/bfin-sim.o bfin/devices.o \
+@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/gui.o bfin/interp.o \
+@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/machs.o bfin/modules.o \
+@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/sim-resume.o
+am_bfin_libsim_a_OBJECTS =
+bfin_libsim_a_OBJECTS = $(am_bfin_libsim_a_OBJECTS)
+bpf_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_DEPENDENCIES = $(patsubst \
+@SIM_ENABLE_ARCH_bpf_TRUE@ %,bpf/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_bpf_TRUE@ %,bpf/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/modules.o bpf/cgen-run.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-scache.o bpf/cgen-trace.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-utils.o bpf/arch.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cpu.o bpf/decode-le.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/decode-be.o bpf/sem-le.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sem-be.o bpf/mloop-le.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-be.o bpf/bpf.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf-helpers.o bpf/sim-if.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/traps.o
+am_bpf_libsim_a_OBJECTS =
+bpf_libsim_a_OBJECTS = $(am_bpf_libsim_a_OBJECTS)
common_libcommon_a_AR = $(AR) $(ARFLAGS)
common_libcommon_a_LIBADD =
am_common_libcommon_a_OBJECTS = common/callback.$(OBJEXT) \
common/target-newlib-syscall.$(OBJEXT) \
common/version.$(OBJEXT)
common_libcommon_a_OBJECTS = $(am_common_libcommon_a_OBJECTS)
+cr16_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_cr16_TRUE@cr16_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_cr16_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_cr16_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_cr16_TRUE@ %,cr16/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_cr16_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_cr16_TRUE@ %,cr16/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/interp.o cr16/modules.o \
+@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/sim-resume.o cr16/simops.o \
+@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/table.o
+am_cr16_libsim_a_OBJECTS =
+cr16_libsim_a_OBJECTS = $(am_cr16_libsim_a_OBJECTS)
+cris_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_cris_TRUE@cris_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_cris_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_cris_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_cris_TRUE@ %,cris/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_cris_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_cris_TRUE@ %,cris/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_cris_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_cris_TRUE@ %,cris/dv-%.o,$(cris_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/modules.o cris/cgen-run.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-scache.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-trace.o cris/cgen-utils.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/arch.o cris/crisv10f.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/cpuv10.o cris/decodev10.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/modelv10.o cris/mloopv10f.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/crisv32f.o cris/cpuv32.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/decodev32.o cris/modelv32.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv32f.o cris/sim-if.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/traps.o
+am_cris_libsim_a_OBJECTS =
+cris_libsim_a_OBJECTS = $(am_cris_libsim_a_OBJECTS)
+d10v_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_d10v_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/interp.o $(patsubst \
+@SIM_ENABLE_ARCH_d10v_TRUE@ %,d10v/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_d10v_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_d10v_TRUE@ %,d10v/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/endian.o d10v/modules.o \
+@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/sim-resume.o d10v/simops.o \
+@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/table.o
+am_d10v_libsim_a_OBJECTS =
+d10v_libsim_a_OBJECTS = $(am_d10v_libsim_a_OBJECTS)
+erc32_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_erc32_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/erc32.o erc32/exec.o \
+@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/float.o erc32/func.o \
+@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/help.o erc32/interf.o \
+@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/modules.o
+am_erc32_libsim_a_OBJECTS =
+erc32_libsim_a_OBJECTS = $(am_erc32_libsim_a_OBJECTS)
+example_synacor_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_examples_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_examples_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_examples_TRUE@ %,example-synacor/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_examples_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_examples_TRUE@ %,example-synacor/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/interp.o \
+@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/modules.o \
+@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/sim-main.o \
+@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/sim-resume.o
+am_example_synacor_libsim_a_OBJECTS =
+example_synacor_libsim_a_OBJECTS = \
+ $(am_example_synacor_libsim_a_OBJECTS)
+frv_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_frv_TRUE@frv_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_frv_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_frv_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_frv_TRUE@ %,frv/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_frv_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_frv_TRUE@ %,frv/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/modules.o frv/cgen-accfp.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-fpu.o frv/cgen-run.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-scache.o frv/cgen-trace.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-utils.o frv/arch.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-par.o frv/cpu.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/decode.o frv/frv.o frv/mloop.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/model.o frv/sem.o frv/cache.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/interrupts.o frv/memory.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/options.o frv/pipeline.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile.o frv/profile-fr400.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr450.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr500.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr550.o frv/registers.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/reset.o frv/sim-if.o frv/traps.o
+am_frv_libsim_a_OBJECTS =
+frv_libsim_a_OBJECTS = $(am_frv_libsim_a_OBJECTS)
+ft32_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_ft32_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_ft32_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_ft32_TRUE@ %,ft32/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_ft32_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_ft32_TRUE@ %,ft32/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/interp.o ft32/modules.o \
+@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/sim-resume.o
+am_ft32_libsim_a_OBJECTS =
+ft32_libsim_a_OBJECTS = $(am_ft32_libsim_a_OBJECTS)
+h8300_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_h8300_TRUE@h8300_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_h8300_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/compile.o $(patsubst \
+@SIM_ENABLE_ARCH_h8300_TRUE@ %,h8300/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_h8300_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_h8300_TRUE@ %,h8300/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/modules.o h8300/sim-resume.o
+am_h8300_libsim_a_OBJECTS =
+h8300_libsim_a_OBJECTS = $(am_h8300_libsim_a_OBJECTS)
igen_libigen_a_AR = $(AR) $(ARFLAGS)
igen_libigen_a_LIBADD =
@SIM_ENABLE_IGEN_TRUE@am_igen_libigen_a_OBJECTS = \
@SIM_ENABLE_IGEN_TRUE@ igen/gen-engine.$(OBJEXT) \
@SIM_ENABLE_IGEN_TRUE@ igen/gen.$(OBJEXT)
igen_libigen_a_OBJECTS = $(am_igen_libigen_a_OBJECTS)
+iq2000_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ %,iq2000/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ %,iq2000/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/modules.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-run.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-scache.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-trace.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-utils.o iq2000/arch.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cpu.o iq2000/decode.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/iq2000.o iq2000/sem.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/mloop.o iq2000/model.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/sim-if.o
+am_iq2000_libsim_a_OBJECTS =
+iq2000_libsim_a_OBJECTS = $(am_iq2000_libsim_a_OBJECTS)
+lm32_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_lm32_TRUE@ %,lm32/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_lm32_TRUE@ %,lm32/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_lm32_TRUE@ %,lm32/dv-%.o,$(lm32_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/modules.o lm32/cgen-run.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-scache.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-trace.o lm32/cgen-utils.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/arch.o lm32/cpu.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/decode.o lm32/sem.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/mloop.o lm32/model.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/lm32.o lm32/sim-if.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/traps.o lm32/user.o
+am_lm32_libsim_a_OBJECTS =
+lm32_libsim_a_OBJECTS = $(am_lm32_libsim_a_OBJECTS)
+m32c_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_m32c_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/gdb-if.o m32c/int.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/load.o m32c/m32c.o m32c/mem.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/misc.o m32c/modules.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.o m32c/reg.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/srcdest.o m32c/syscalls.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/trace.o
+am_m32c_libsim_a_OBJECTS =
+m32c_libsim_a_OBJECTS = $(am_m32c_libsim_a_OBJECTS)
+m32r_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_m32r_TRUE@ %,m32r/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_m32r_TRUE@ %,m32r/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_m32r_TRUE@ %,m32r/dv-%.o,$(m32r_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modules.o m32r/cgen-run.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-scache.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-trace.o m32r/cgen-utils.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/arch.o m32r/m32r.o m32r/cpu.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decode.o m32r/sem.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model.o m32r/mloop.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32rx.o m32r/cpux.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decodex.o m32r/modelx.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloopx.o m32r/m32r2.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpu2.o m32r/decode2.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model2.o m32r/mloop2.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/sim-if.o m32r/traps.o
+am_m32r_libsim_a_OBJECTS =
+m32r_libsim_a_OBJECTS = $(am_m32r_libsim_a_OBJECTS)
+m68hc11_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/interp.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11int.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc12int.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/emulos.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/interrupts.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11_sim.o $(patsubst \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ %,m68hc11/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ %,m68hc11/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ %,m68hc11/dv-%.o,$(m68hc11_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/modules.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/sim-resume.o
+am_m68hc11_libsim_a_OBJECTS =
+m68hc11_libsim_a_OBJECTS = $(am_m68hc11_libsim_a_OBJECTS)
+mcore_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_mcore_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/interp.o $(patsubst \
+@SIM_ENABLE_ARCH_mcore_TRUE@ %,mcore/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_mcore_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_mcore_TRUE@ %,mcore/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/modules.o mcore/sim-resume.o
+am_mcore_libsim_a_OBJECTS =
+mcore_libsim_a_OBJECTS = $(am_mcore_libsim_a_OBJECTS)
+microblaze_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_DEPENDENCIES = $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/interp.o \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ %,microblaze/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ %,microblaze/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/modules.o \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/sim-resume.o
+am_microblaze_libsim_a_OBJECTS =
+microblaze_libsim_a_OBJECTS = $(am_microblaze_libsim_a_OBJECTS)
+mips_libsim_a_AR = $(AR) $(ARFLAGS)
+am__DEPENDENCIES_1 =
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__DEPENDENCIES_2 = $(am__DEPENDENCIES_1) \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o
+@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_88) \
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- $(am__append_76) $(am__append_82) $(am__append_88) \
- $(am__append_98) $(am__append_102)
+ site-sim-config.exp testrun.log testrun.sum $(am__append_21) \
+ $(am__append_27) $(am__append_34) $(am__append_40) \
+ $(am__append_51) $(am__append_60) $(am__append_66) \
+ $(am__append_71) $(am__append_77) $(am__append_83) \
+ $(am__append_99) $(am__append_106) $(am__append_112) \
+ $(am__append_122) $(am__append_126)
AM_CFLAGS = $(WERROR_CFLAGS) $(WARN_CFLAGS)
AM_CPPFLAGS = $(INCGNU) -I$(srcroot)/include -I../bfd -I.. \
$(SIM_HW_CFLAGS) $(SIM_INLINE) -I$(srcdir)/common \
LINK_FOR_BUILD = $(CC_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(LDFLAGS_FOR_BUILD) -o $@
SIM_ALL_RECURSIVE_DEPS = common/libcommon.a \
$(common_HW_CONFIG_H_TARGETS) $(common_GEN_MODULES_C_TARGETS) \
- $(am__append_4) $(am__append_16) $(am__append_20) \
- $(am__append_27) $(am__append_31) $(am__append_40) \
- $(am__append_46) $(am__append_51) $(am__append_54) \
- $(am__append_60) $(am__append_64) $(am__append_75) \
- $(am__append_81) $(am__append_87) $(am__append_96) \
- $(am__append_101)
+ $(am__append_4) $(am__append_20) $(am__append_25) \
+ $(am__append_33) $(am__append_38) $(am__append_50) \
+ $(am__append_59) $(am__append_65) $(am__append_69) \
+ $(am__append_76) $(am__append_81) $(am__append_98) \
+ $(am__append_105) $(am__append_111) $(am__append_120) \
+ $(am__append_125)
SIM_INSTALL_DATA_LOCAL_DEPS =
-SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_35)
-SIM_UNINSTALL_LOCAL_DEPS = $(am__append_36)
+SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_43)
+SIM_UNINSTALL_LOCAL_DEPS = $(am__append_44)
common_libcommon_a_SOURCES = \
common/callback.c \
common/portability.c \
@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/libsim.a \
@SIM_ENABLE_ARCH_aarch64_TRUE@ $(SIM_COMMON_LIBS)
+@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_arm_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_arm_TRUE@ arm/wrapper.o \
+@SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst %,arm/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst %,arm/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_arm_TRUE@ arm/armemu.o \
+@SIM_ENABLE_ARCH_arm_TRUE@ arm/armemu32.o arm/arminit.o arm/armos.o arm/armsupp.o \
+@SIM_ENABLE_ARCH_arm_TRUE@ arm/armvirt.o arm/thumbemu.o \
+@SIM_ENABLE_ARCH_arm_TRUE@ arm/armcopro.o arm/maverick.o arm/iwmmxt.o \
+@SIM_ENABLE_ARCH_arm_TRUE@ arm/modules.o
+
@SIM_ENABLE_ARCH_arm_TRUE@arm_run_SOURCES =
@SIM_ENABLE_ARCH_arm_TRUE@arm_run_LDADD = \
@SIM_ENABLE_ARCH_arm_TRUE@ arm/nrun.o \
@SIM_ENABLE_ARCH_arm_TRUE@armdocdir = $(docdir)/arm
@SIM_ENABLE_ARCH_arm_TRUE@armdoc_DATA = arm/README
+@SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_avr_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_avr_TRUE@ avr/interp.o \
+@SIM_ENABLE_ARCH_avr_TRUE@ $(patsubst %,avr/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_avr_TRUE@ $(patsubst %,avr/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_avr_TRUE@ avr/modules.o \
+@SIM_ENABLE_ARCH_avr_TRUE@ avr/sim-resume.o
+
@SIM_ENABLE_ARCH_avr_TRUE@avr_run_SOURCES =
@SIM_ENABLE_ARCH_avr_TRUE@avr_run_LDADD = \
@SIM_ENABLE_ARCH_avr_TRUE@ avr/nrun.o \
@SIM_ENABLE_ARCH_avr_TRUE@ avr/libsim.a \
@SIM_ENABLE_ARCH_avr_TRUE@ $(SIM_COMMON_LIBS)
+@SIM_ENABLE_ARCH_bfin_TRUE@bfin_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_bfin_TRUE@bfin_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_bfin_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_bfin_TRUE@ $(patsubst %,bfin/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_bfin_TRUE@ $(patsubst %,bfin/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_bfin_TRUE@ $(patsubst %,bfin/dv-%.o,$(bfin_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/bfin-sim.o \
+@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/devices.o \
+@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/gui.o \
+@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/interp.o \
+@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/machs.o \
+@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/modules.o \
+@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/sim-resume.o
+
@SIM_ENABLE_ARCH_bfin_TRUE@bfin_run_SOURCES =
@SIM_ENABLE_ARCH_bfin_TRUE@bfin_run_LDADD = \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/nrun.o \
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_wp \
@SIM_ENABLE_ARCH_bfin_TRUE@ eth_phy
+@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_bpf_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst %,bpf/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst %,bpf/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/modules.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-run.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-scache.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-trace.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-utils.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/arch.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cpu.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/decode-le.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/decode-be.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sem-le.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sem-be.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-le.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-be.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf-helpers.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sim-if.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/traps.o
+
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_SOURCES =
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_LDADD = \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/nrun.o \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-be.c \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/stamp-mloop-be
+@SIM_ENABLE_ARCH_cr16_TRUE@cr16_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_cr16_TRUE@cr16_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_cr16_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_cr16_TRUE@ $(patsubst %,cr16/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_cr16_TRUE@ $(patsubst %,cr16/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/interp.o \
+@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/modules.o \
+@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/sim-resume.o \
+@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/simops.o \
+@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/table.o
+
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_run_SOURCES =
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_run_LDADD = \
@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/nrun.o \
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_SOURCES = cr16/gencode.c
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_LDADD = cr16/cr16-opc.o
+@SIM_ENABLE_ARCH_cris_TRUE@cris_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_cris_TRUE@cris_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_cris_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_cris_TRUE@ $(patsubst %,cris/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_cris_TRUE@ $(patsubst %,cris/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_cris_TRUE@ $(patsubst %,cris/dv-%.o,$(cris_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/modules.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-run.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-scache.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-trace.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-utils.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/arch.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/crisv10f.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/cpuv10.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/decodev10.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/modelv10.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv10f.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/crisv32f.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/cpuv32.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/decodev32.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/modelv32.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv32f.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/sim-if.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/traps.o
+
@SIM_ENABLE_ARCH_cris_TRUE@cris_run_SOURCES =
@SIM_ENABLE_ARCH_cris_TRUE@cris_run_LDADD = \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/nrun.o \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv32f.c \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/stamp-mloop-v32f
+@SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_d10v_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/interp.o \
+@SIM_ENABLE_ARCH_d10v_TRUE@ $(patsubst %,d10v/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_d10v_TRUE@ $(patsubst %,d10v/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/endian.o \
+@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/modules.o \
+@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/sim-resume.o \
+@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/simops.o \
+@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/table.o
+
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_SOURCES =
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_LDADD = \
@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/nrun.o \
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_SOURCES = d10v/gencode.c
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_LDADD = d10v/d10v-opc.o
+@SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_erc32_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/erc32.o \
+@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/exec.o \
+@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/float.o \
+@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/func.o \
+@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/help.o \
+@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/interf.o \
+@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/modules.o
+
@SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_SOURCES =
@SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_LDADD = \
@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/sis.o \
@SIM_ENABLE_ARCH_erc32_TRUE@erc32docdir = $(docdir)/erc32
@SIM_ENABLE_ARCH_erc32_TRUE@erc32doc_DATA = erc32/README.erc32 erc32/README.gdb erc32/README.sis
+@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_examples_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_examples_TRUE@ $(patsubst %,example-synacor/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_examples_TRUE@ $(patsubst %,example-synacor/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/interp.o \
+@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/modules.o \
+@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/sim-main.o \
+@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/sim-resume.o
+
@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_SOURCES =
@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_LDADD = \
@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/nrun.o \
@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/libsim.a \
@SIM_ENABLE_ARCH_examples_TRUE@ $(SIM_COMMON_LIBS)
+@SIM_ENABLE_ARCH_frv_TRUE@frv_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_frv_TRUE@frv_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_frv_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_frv_TRUE@ $(patsubst %,frv/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_frv_TRUE@ $(patsubst %,frv/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/modules.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-accfp.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-fpu.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-run.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-scache.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-trace.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-utils.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/arch.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-par.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/cpu.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/decode.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/frv.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/mloop.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/model.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/sem.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/cache.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/interrupts.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/memory.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/options.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/pipeline.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr400.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr450.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr500.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr550.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/registers.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/reset.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/sim-if.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/traps.o
+
@SIM_ENABLE_ARCH_frv_TRUE@frv_run_SOURCES =
@SIM_ENABLE_ARCH_frv_TRUE@frv_run_LDADD = \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/nrun.o \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/mloop.c \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/stamp-mloop
+@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_ft32_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_ft32_TRUE@ $(patsubst %,ft32/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_ft32_TRUE@ $(patsubst %,ft32/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/interp.o \
+@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/modules.o \
+@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/sim-resume.o
+
@SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_SOURCES =
@SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_LDADD = \
@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/nrun.o \
@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/libsim.a \
@SIM_ENABLE_ARCH_ft32_TRUE@ $(SIM_COMMON_LIBS)
+@SIM_ENABLE_ARCH_h8300_TRUE@h8300_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_h8300_TRUE@h8300_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_h8300_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/compile.o \
+@SIM_ENABLE_ARCH_h8300_TRUE@ $(patsubst %,h8300/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_h8300_TRUE@ $(patsubst %,h8300/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/modules.o \
+@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/sim-resume.o
+
@SIM_ENABLE_ARCH_h8300_TRUE@h8300_run_SOURCES =
@SIM_ENABLE_ARCH_h8300_TRUE@h8300_run_LDADD = \
@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/nrun.o \
@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/libsim.a \
@SIM_ENABLE_ARCH_h8300_TRUE@ $(SIM_COMMON_LIBS)
+@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ $(patsubst %,iq2000/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ $(patsubst %,iq2000/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/modules.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-run.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-scache.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-trace.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-utils.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/arch.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cpu.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/decode.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/iq2000.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/sem.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/mloop.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/model.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/sim-if.o
+
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_SOURCES =
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_LDADD = \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/nrun.o \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/mloop.c \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/stamp-mloop
+@SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst %,lm32/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst %,lm32/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst %,lm32/dv-%.o,$(lm32_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/modules.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-run.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-scache.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-trace.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-utils.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/arch.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cpu.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/decode.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/sem.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/mloop.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/model.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/lm32.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/sim-if.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/traps.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/user.o
+
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_SOURCES =
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_LDADD = \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/nrun.o \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/mloop.c \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/stamp-mloop
+@SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_m32c_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/gdb-if.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/int.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/load.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/mem.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/misc.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/modules.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/reg.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/srcdest.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/syscalls.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/trace.o
+
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_SOURCES =
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_LDADD = \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/main.o \
# opc2c leaks memory, and therefore makes AddressSanitizer unhappy. Disable
# leak detection while running it.
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_OPC2C_RUN = ASAN_OPTIONS=detect_leaks=0 m32c/opc2c$(EXEEXT)
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/dv-%.o,$(m32r_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modules.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-run.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-scache.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-trace.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-utils.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/arch.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32r.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpu.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decode.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/sem.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32rx.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpux.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decodex.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modelx.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloopx.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32r2.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpu2.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decode2.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model2.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop2.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/sim-if.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/traps.o
+
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_SOURCES =
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_LDADD = \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/nrun.o \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop2.c \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/stamp-mloop-2
+@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/interp.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11int.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc12int.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/emulos.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/interrupts.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11_sim.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst %,m68hc11/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst %,m68hc11/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst %,m68hc11/dv-%.o,$(m68hc11_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/modules.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/sim-resume.o
+
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_SOURCES =
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_LDADD = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/nrun.o \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc12int.c
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_gencode_SOURCES = m68hc11/gencode.c
+@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_mcore_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/interp.o \
+@SIM_ENABLE_ARCH_mcore_TRUE@ $(patsubst %,mcore/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_mcore_TRUE@ $(patsubst %,mcore/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/modules.o \
+@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/sim-resume.o
+
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_SOURCES =
@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_LDADD = \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/nrun.o \
@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/libsim.a \
@SIM_ENABLE_ARCH_mcore_TRUE@ $(SIM_COMMON_LIBS)
+@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/interp.o \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ $(patsubst %,microblaze/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ $(patsubst %,microblaze/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/modules.o \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/sim-resume.o
+
@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_SOURCES =
@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_LDADD = \
@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/nrun.o \
@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/libsim.a \
@SIM_ENABLE_ARCH_microblaze_TRUE@ $(SIM_COMMON_LIBS)
+@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_88) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_89) $(am__append_90)
+@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/interp.o \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_GEN_OBJ) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst %,mips/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst %,mips/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst %,mips/dv-%.o,$(mips_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/cp1.o \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/dsp.o \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/mdmx.o \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/modules.o \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/sim-main.o \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/sim-resume.o
+
+@SIM_ENABLE_ARCH_mips_TRUE@EXTRA_mips_libsim_a_DEPENDENCIES = $(SIM_MIPS_MULTI_OBJ)
@SIM_ENABLE_ARCH_mips_TRUE@mips_run_SOURCES =
@SIM_ENABLE_ARCH_mips_TRUE@mips_run_LDADD = \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/nrun.o \
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \
-@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_72) $(am__append_73) \
-@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74)
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_95) $(am__append_96) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_97)
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \
@SIM_ENABLE_ARCH_mips_TRUE@mips_M16_DC = $(srcdir)/mips/m16.dc
@SIM_ENABLE_ARCH_mips_TRUE@mips_MICROMIPS32_DC = $(srcdir)/mips/micromips.dc
@SIM_ENABLE_ARCH_mips_TRUE@mips_MICROMIPS16_DC = $(srcdir)/mips/micromips16.dc
+@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_libsim_a_SOURCES =
+@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ $(common_libcommon_a_OBJECTS) \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/irun.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/support.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst %,mn10300/%,$(SIM_NEW_COMMON_OBJS)) \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst %,mn10300/dv-%.o,$(SIM_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst %,mn10300/dv-%.o,$(mn10300_SIM_EXTRA_HW_DEVICES)) \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/interp.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/modules.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/op_utils.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/sim-resume.o
+
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_SOURCES =
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_LDADD = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/nrun.o \
$(AM_V_at)-rm -f aarch64/libsim.a
$(AM_V_AR)$(aarch64_libsim_a_AR) aarch64/libsim.a $(aarch64_libsim_a_OBJECTS) $(aarch64_libsim_a_LIBADD)
$(AM_V_at)$(RANLIB) aarch64/libsim.a
+arm/$(am__dirstamp):
+ @$(MKDIR_P) arm
+ @: > arm/$(am__dirstamp)
+
+arm/libsim.a: $(arm_libsim_a_OBJECTS) $(arm_libsim_a_DEPENDENCIES) $(EXTRA_arm_libsim_a_DEPENDENCIES) arm/$(am__dirstamp)
+ $(AM_V_at)-rm -f arm/libsim.a
+ $(AM_V_AR)$(arm_libsim_a_AR) arm/libsim.a $(arm_libsim_a_OBJECTS) $(arm_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) arm/libsim.a
+avr/$(am__dirstamp):
+ @$(MKDIR_P) avr
+ @: > avr/$(am__dirstamp)
+
+avr/libsim.a: $(avr_libsim_a_OBJECTS) $(avr_libsim_a_DEPENDENCIES) $(EXTRA_avr_libsim_a_DEPENDENCIES) avr/$(am__dirstamp)
+ $(AM_V_at)-rm -f avr/libsim.a
+ $(AM_V_AR)$(avr_libsim_a_AR) avr/libsim.a $(avr_libsim_a_OBJECTS) $(avr_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) avr/libsim.a
+bfin/$(am__dirstamp):
+ @$(MKDIR_P) bfin
+ @: > bfin/$(am__dirstamp)
+
+bfin/libsim.a: $(bfin_libsim_a_OBJECTS) $(bfin_libsim_a_DEPENDENCIES) $(EXTRA_bfin_libsim_a_DEPENDENCIES) bfin/$(am__dirstamp)
+ $(AM_V_at)-rm -f bfin/libsim.a
+ $(AM_V_AR)$(bfin_libsim_a_AR) bfin/libsim.a $(bfin_libsim_a_OBJECTS) $(bfin_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) bfin/libsim.a
+bpf/$(am__dirstamp):
+ @$(MKDIR_P) bpf
+ @: > bpf/$(am__dirstamp)
+
+bpf/libsim.a: $(bpf_libsim_a_OBJECTS) $(bpf_libsim_a_DEPENDENCIES) $(EXTRA_bpf_libsim_a_DEPENDENCIES) bpf/$(am__dirstamp)
+ $(AM_V_at)-rm -f bpf/libsim.a
+ $(AM_V_AR)$(bpf_libsim_a_AR) bpf/libsim.a $(bpf_libsim_a_OBJECTS) $(bpf_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) bpf/libsim.a
common/$(am__dirstamp):
@$(MKDIR_P) common
@: > common/$(am__dirstamp)
$(AM_V_at)-rm -f common/libcommon.a
$(AM_V_AR)$(common_libcommon_a_AR) common/libcommon.a $(common_libcommon_a_OBJECTS) $(common_libcommon_a_LIBADD)
$(AM_V_at)$(RANLIB) common/libcommon.a
+cr16/$(am__dirstamp):
+ @$(MKDIR_P) cr16
+ @: > cr16/$(am__dirstamp)
+
+cr16/libsim.a: $(cr16_libsim_a_OBJECTS) $(cr16_libsim_a_DEPENDENCIES) $(EXTRA_cr16_libsim_a_DEPENDENCIES) cr16/$(am__dirstamp)
+ $(AM_V_at)-rm -f cr16/libsim.a
+ $(AM_V_AR)$(cr16_libsim_a_AR) cr16/libsim.a $(cr16_libsim_a_OBJECTS) $(cr16_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) cr16/libsim.a
+cris/$(am__dirstamp):
+ @$(MKDIR_P) cris
+ @: > cris/$(am__dirstamp)
+
+cris/libsim.a: $(cris_libsim_a_OBJECTS) $(cris_libsim_a_DEPENDENCIES) $(EXTRA_cris_libsim_a_DEPENDENCIES) cris/$(am__dirstamp)
+ $(AM_V_at)-rm -f cris/libsim.a
+ $(AM_V_AR)$(cris_libsim_a_AR) cris/libsim.a $(cris_libsim_a_OBJECTS) $(cris_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) cris/libsim.a
+d10v/$(am__dirstamp):
+ @$(MKDIR_P) d10v
+ @: > d10v/$(am__dirstamp)
+
+d10v/libsim.a: $(d10v_libsim_a_OBJECTS) $(d10v_libsim_a_DEPENDENCIES) $(EXTRA_d10v_libsim_a_DEPENDENCIES) d10v/$(am__dirstamp)
+ $(AM_V_at)-rm -f d10v/libsim.a
+ $(AM_V_AR)$(d10v_libsim_a_AR) d10v/libsim.a $(d10v_libsim_a_OBJECTS) $(d10v_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) d10v/libsim.a
+erc32/$(am__dirstamp):
+ @$(MKDIR_P) erc32
+ @: > erc32/$(am__dirstamp)
+
+erc32/libsim.a: $(erc32_libsim_a_OBJECTS) $(erc32_libsim_a_DEPENDENCIES) $(EXTRA_erc32_libsim_a_DEPENDENCIES) erc32/$(am__dirstamp)
+ $(AM_V_at)-rm -f erc32/libsim.a
+ $(AM_V_AR)$(erc32_libsim_a_AR) erc32/libsim.a $(erc32_libsim_a_OBJECTS) $(erc32_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) erc32/libsim.a
+example-synacor/$(am__dirstamp):
+ @$(MKDIR_P) example-synacor
+ @: > example-synacor/$(am__dirstamp)
+
+example-synacor/libsim.a: $(example_synacor_libsim_a_OBJECTS) $(example_synacor_libsim_a_DEPENDENCIES) $(EXTRA_example_synacor_libsim_a_DEPENDENCIES) example-synacor/$(am__dirstamp)
+ $(AM_V_at)-rm -f example-synacor/libsim.a
+ $(AM_V_AR)$(example_synacor_libsim_a_AR) example-synacor/libsim.a $(example_synacor_libsim_a_OBJECTS) $(example_synacor_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) example-synacor/libsim.a
+frv/$(am__dirstamp):
+ @$(MKDIR_P) frv
+ @: > frv/$(am__dirstamp)
+
+frv/libsim.a: $(frv_libsim_a_OBJECTS) $(frv_libsim_a_DEPENDENCIES) $(EXTRA_frv_libsim_a_DEPENDENCIES) frv/$(am__dirstamp)
+ $(AM_V_at)-rm -f frv/libsim.a
+ $(AM_V_AR)$(frv_libsim_a_AR) frv/libsim.a $(frv_libsim_a_OBJECTS) $(frv_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) frv/libsim.a
+ft32/$(am__dirstamp):
+ @$(MKDIR_P) ft32
+ @: > ft32/$(am__dirstamp)
+
+ft32/libsim.a: $(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_DEPENDENCIES) $(EXTRA_ft32_libsim_a_DEPENDENCIES) ft32/$(am__dirstamp)
+ $(AM_V_at)-rm -f ft32/libsim.a
+ $(AM_V_AR)$(ft32_libsim_a_AR) ft32/libsim.a $(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) ft32/libsim.a
+h8300/$(am__dirstamp):
+ @$(MKDIR_P) h8300
+ @: > h8300/$(am__dirstamp)
+
+h8300/libsim.a: $(h8300_libsim_a_OBJECTS) $(h8300_libsim_a_DEPENDENCIES) $(EXTRA_h8300_libsim_a_DEPENDENCIES) h8300/$(am__dirstamp)
+ $(AM_V_at)-rm -f h8300/libsim.a
+ $(AM_V_AR)$(h8300_libsim_a_AR) h8300/libsim.a $(h8300_libsim_a_OBJECTS) $(h8300_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) h8300/libsim.a
igen/$(am__dirstamp):
@$(MKDIR_P) igen
@: > igen/$(am__dirstamp)
@SIM_ENABLE_IGEN_FALSE@ $(AM_V_at)-rm -f igen/libigen.a
@SIM_ENABLE_IGEN_FALSE@ $(AM_V_AR)$(igen_libigen_a_AR) igen/libigen.a $(igen_libigen_a_OBJECTS) $(igen_libigen_a_LIBADD)
@SIM_ENABLE_IGEN_FALSE@ $(AM_V_at)$(RANLIB) igen/libigen.a
+iq2000/$(am__dirstamp):
+ @$(MKDIR_P) iq2000
+ @: > iq2000/$(am__dirstamp)
+
+iq2000/libsim.a: $(iq2000_libsim_a_OBJECTS) $(iq2000_libsim_a_DEPENDENCIES) $(EXTRA_iq2000_libsim_a_DEPENDENCIES) iq2000/$(am__dirstamp)
+ $(AM_V_at)-rm -f iq2000/libsim.a
+ $(AM_V_AR)$(iq2000_libsim_a_AR) iq2000/libsim.a $(iq2000_libsim_a_OBJECTS) $(iq2000_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) iq2000/libsim.a
+lm32/$(am__dirstamp):
+ @$(MKDIR_P) lm32
+ @: > lm32/$(am__dirstamp)
+
+lm32/libsim.a: $(lm32_libsim_a_OBJECTS) $(lm32_libsim_a_DEPENDENCIES) $(EXTRA_lm32_libsim_a_DEPENDENCIES) lm32/$(am__dirstamp)
+ $(AM_V_at)-rm -f lm32/libsim.a
+ $(AM_V_AR)$(lm32_libsim_a_AR) lm32/libsim.a $(lm32_libsim_a_OBJECTS) $(lm32_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) lm32/libsim.a
+m32c/$(am__dirstamp):
+ @$(MKDIR_P) m32c
+ @: > m32c/$(am__dirstamp)
+
+m32c/libsim.a: $(m32c_libsim_a_OBJECTS) $(m32c_libsim_a_DEPENDENCIES) $(EXTRA_m32c_libsim_a_DEPENDENCIES) m32c/$(am__dirstamp)
+ $(AM_V_at)-rm -f m32c/libsim.a
+ $(AM_V_AR)$(m32c_libsim_a_AR) m32c/libsim.a $(m32c_libsim_a_OBJECTS) $(m32c_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) m32c/libsim.a
+m32r/$(am__dirstamp):
+ @$(MKDIR_P) m32r
+ @: > m32r/$(am__dirstamp)
+
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+
+@SIM_ENABLE_ARCH_examples_TRUE@example-synacor/%.o: common/%.c
+@SIM_ENABLE_ARCH_examples_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_frv_TRUE@$(frv_libsim_a_OBJECTS) $(frv_libsim_a_LIBADD): frv/hw-config.h
+
+@SIM_ENABLE_ARCH_frv_TRUE@frv/%.o: frv/%.c
+@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_frv_TRUE@frv/%.o: common/%.c
+@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_frv_TRUE@frv/modules.c: | $(frv_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_frv_TRUE@frv/mloop.c frv/eng.h: frv/stamp-mloop ; @true
@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-cpu-decode:
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_frv_TRUE@frv/cpu.h frv/sem.c frv/model.c frv/decode.c frv/decode.h: @CGEN_MAINT@ frv/cgen-cpu-decode
+@SIM_ENABLE_ARCH_ft32_TRUE@$(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_LIBADD): ft32/hw-config.h
+
+@SIM_ENABLE_ARCH_ft32_TRUE@ft32/%.o: ft32/%.c
+@SIM_ENABLE_ARCH_ft32_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_ft32_TRUE@ft32/%.o: common/%.c
+@SIM_ENABLE_ARCH_ft32_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_h8300_TRUE@$(h8300_libsim_a_OBJECTS) $(h8300_libsim_a_LIBADD): h8300/hw-config.h
+
+@SIM_ENABLE_ARCH_h8300_TRUE@h8300/%.o: h8300/%.c
+@SIM_ENABLE_ARCH_h8300_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_h8300_TRUE@h8300/%.o: common/%.c
+@SIM_ENABLE_ARCH_h8300_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_iq2000_TRUE@$(iq2000_libsim_a_OBJECTS) $(iq2000_libsim_a_LIBADD): iq2000/hw-config.h
+
+@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/%.o: iq2000/%.c
+@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/%.o: common/%.c
+@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/modules.c: | $(iq2000_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/mloop.c iq2000/eng.h: iq2000/stamp-mloop ; @true
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cgen-cpu-decode:
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)cpu=iq2000bf mach=iq2000 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cpu.h iq2000/sem.c iq2000/sem-switch.c iq2000/model.c iq2000/decode.c iq2000/decode.h: @CGEN_MAINT@ iq2000/cgen-cpu-decode
+@SIM_ENABLE_ARCH_lm32_TRUE@$(lm32_libsim_a_OBJECTS) $(lm32_libsim_a_LIBADD): lm32/hw-config.h
+
+@SIM_ENABLE_ARCH_lm32_TRUE@lm32/%.o: lm32/%.c
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_lm32_TRUE@lm32/%.o: common/%.c
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/modules.c: | $(lm32_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/mloop.c lm32/eng.h: lm32/stamp-mloop ; @true
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cgen-cpu-decode:
@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_GEN)cpu=lm32bf mach=lm32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cpu.h lm32/sem.c lm32/sem-switch.c lm32/model.c lm32/decode.c lm32/decode.h: @CGEN_MAINT@ lm32/cgen-cpu-decode
+@SIM_ENABLE_ARCH_m32c_TRUE@$(m32c_libsim_a_OBJECTS) $(m32c_libsim_a_LIBADD): m32c/hw-config.h
-@SIM_ENABLE_ARCH_m32c_TRUE@m32c/%.o: m32c/%.c | m32c/libsim.a $(SIM_ALL_RECURSIVE_DEPS)
-@SIM_ENABLE_ARCH_m32c_TRUE@ $(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_m32c_TRUE@m32c/%.o: m32c/%.c
+@SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_m32c_TRUE@m32c/%.o: common/%.c
+@SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_m32c_TRUE@m32c/modules.c: | $(m32c_BUILD_OUTPUTS)
# These rules are copied from automake, but tweaked to use FOR_BUILD variables.
@SIM_ENABLE_ARCH_m32c_TRUE@m32c/r8c.c: m32c/r8c.opc m32c/opc2c$(EXEEXT)
@SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_GEN)$(m32c_OPC2C_RUN) -l $@.log $< > $@.tmp
@SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_at)mv $@.tmp $@
+@SIM_ENABLE_ARCH_m32r_TRUE@$(m32r_libsim_a_OBJECTS) $(m32r_libsim_a_LIBADD): m32r/hw-config.h
+
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r/%.o: m32r/%.c
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r/%.o: common/%.c
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/modules.c: | $(m32r_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop.c m32r/eng.h: m32r/stamp-mloop ; @true
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode-2:
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)cpu=m32r2f mach=m32r2 SUFFIX=2 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cpu2.h m32r/sem2-switch.c m32r/model2.c m32r/decode2.c m32r/decode2.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-2
+@SIM_ENABLE_ARCH_m68hc11_TRUE@$(m68hc11_libsim_a_OBJECTS) $(m68hc11_libsim_a_LIBADD): m68hc11/hw-config.h
+
+@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/%.o: m68hc11/%.c
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/%.o: common/%.c
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/modules.c: | $(m68hc11_BUILD_OUTPUTS)
# These rules are copied from automake, but tweaked to use FOR_BUILD variables.
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/m68hc12int.c: m68hc11/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(AM_V_GEN)$< -m6812 >$@
+@SIM_ENABLE_ARCH_mcore_TRUE@$(mcore_libsim_a_OBJECTS) $(mcore_libsim_a_LIBADD): mcore/hw-config.h
+
+@SIM_ENABLE_ARCH_mcore_TRUE@mcore/%.o: mcore/%.c
+@SIM_ENABLE_ARCH_mcore_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_mcore_TRUE@mcore/%.o: common/%.c
+@SIM_ENABLE_ARCH_mcore_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_microblaze_TRUE@$(microblaze_libsim_a_OBJECTS) $(microblaze_libsim_a_LIBADD): microblaze/hw-config.h
+
+@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze/%.o: microblaze/%.c
+@SIM_ENABLE_ARCH_microblaze_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze/%.o: common/%.c
+@SIM_ENABLE_ARCH_microblaze_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_mips_TRUE@$(mips_libsim_a_OBJECTS) $(mips_libsim_a_LIBADD): mips/hw-config.h
+
+@SIM_ENABLE_ARCH_mips_TRUE@mips/%.o: mips/%.c
+@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_mips_TRUE@mips/%.o: common/%.c
+@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_mips_TRUE@mips/modules.c: | $(mips_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_IGEN_ITABLE): mips/stamp-igen-itable
@SIM_ENABLE_ARCH_mips_TRUE@ esac \
@SIM_ENABLE_ARCH_mips_TRUE@ done
@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)touch $@
+@SIM_ENABLE_ARCH_mn10300_TRUE@$(mn10300_libsim_a_OBJECTS) $(mn10300_libsim_a_LIBADD): mn10300/hw-config.h
+
+@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/%.o: mn10300/%.c
+@SIM_ENABLE_ARCH_mn10300_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+
+@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/%.o: common/%.c
+@SIM_ENABLE_ARCH_mn10300_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/modules.c: | $(mn10300_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_mn10300_TRUE@$(mn10300_BUILT_SRC_FROM_IGEN): mn10300/stamp-igen
projects / binutils-gdb.git / blobdiff